comparator_4.fnsim.qmsg

大量VHDL写的数字系统设计有用实例达到

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Functional Simulation Netlist Generation Quartus II " "Info: Running Quartus II Functional Simulation Netlist Generation" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.0 Build 33 02/05/2007 SJ Full Version " "Info: Version 7.0 Build 33 02/05/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu May 31 17:08:31 2007 " "Info: Processing started: Thu May 31 17:08:31 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off comparator_4 -c comparator_4 --generate_functional_sim_netlist " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off comparator_4 -c comparator_4 --generate_functional_sim_netlist" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "comparator_4.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file comparator_4.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 comparator_4-one " "Info: Found design unit 1: comparator_4-one" {  } { { "comparator_4.vhd" "" { Text "D:/my_eda/comparator_4/comparator_4.vhd" 7 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 comparator_4 " "Info: Found entity 1: comparator_4" {  } { { "comparator_4.vhd" "" { Text "D:/my_eda/comparator_4/comparator_4.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "comparator_4 " "Info: Elaborating entity \"comparator_4\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "y1 comparator_4.vhd(9) " "Warning (10631): VHDL Process Statement warning at comparator_4.vhd(9): inferring latch(es) for signal or variable \"y1\", which holds its previous value in one or more paths through the process" {  } { { "comparator_4.vhd" "" { Text "D:/my_eda/comparator_4/comparator_4.vhd" 9 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "y2 comparator_4.vhd(9) " "Warning (10631): VHDL Process Statement warning at comparator_4.vhd(9): inferring latch(es) for signal or variable \"y2\", which holds its previous value in one or more paths through the process" {  } { { "comparator_4.vhd" "" { Text "D:/my_eda/comparator_4/comparator_4.vhd" 9 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "y3 comparator_4.vhd(9) " "Warning (10631): VHDL Process Statement warning at comparator_4.vhd(9): inferring latch(es) for signal or variable \"y3\", which holds its previous value in one or more paths through the process" {  } { { "comparator_4.vhd" "" { Text "D:/my_eda/comparator_4/comparator_4.vhd" 9 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "y3 comparator_4.vhd(9) " "Info (10041): Verilog HDL or VHDL info at comparator_4.vhd(9): inferred latch for \"y3\"" {  } { { "comparator_4.vhd" "" { Text "D:/my_eda/comparator_4/comparator_4.vhd" 9 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "y2 comparator_4.vhd(9) " "Info (10041): Verilog HDL or VHDL info at comparator_4.vhd(9): inferred latch for \"y2\"" {  } { { "comparator_4.vhd" "" { Text "D:/my_eda/comparator_4/comparator_4.vhd" 9 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "y1 comparator_4.vhd(9) " "Info (10041): Verilog HDL or VHDL info at comparator_4.vhd(9): inferred latch for \"y1\"" {  } { { "comparator_4.vhd" "" { Text "D:/my_eda/comparator_4/comparator_4.vhd" 9 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Functional Simulation Netlist Generation 0 s 3 s Quartus II " "Info: Quartus II Functional Simulation Netlist Generation was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "135 " "Info: Allocated 135 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu May 31 17:08:36 2007 " "Info: Processing ended: Thu May 31 17:08:36 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}