maichong.tan.rpt

大量VHDL写的数字系统设计有用实例达到

; N/A   ; None         ; 4.276 ns   ; clr  ; x[0] ; clk      ;
+-------+--------------+------------+------+------+----------+


+------------------------------------------------------------+
; tco                                                        ;
+-------+--------------+------------+------+----+------------+
; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
+-------+--------------+------------+------+----+------------+
; N/A   ; None         ; 7.306 ns   ; x[2] ; q1 ; clk        ;
; N/A   ; None         ; 7.054 ns   ; y[2] ; q2 ; clk        ;
; N/A   ; None         ; 7.054 ns   ; x[1] ; q0 ; clk        ;
+-------+--------------+------------+------+----+------------+


+------------------------------------------------------------------+
; th                                                               ;
+---------------+-------------+-----------+------+------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To   ; To Clock ;
+---------------+-------------+-----------+------+------+----------+
; N/A           ; None        ; -4.010 ns ; clr  ; x[0] ; clk      ;
; N/A           ; None        ; -4.060 ns ; clr  ; x[1] ; clk      ;
; N/A           ; None        ; -4.060 ns ; clr  ; x[2] ; clk      ;
; N/A           ; None        ; -4.061 ns ; clr  ; y[2] ; clk      ;
+---------------+-------------+-----------+------+------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version
    Info: Processing started: Wed Mar 21 19:52:45 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off maichong -c maichong --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 340.02 MHz between source register "x[2]" and destination register "x[0]"
    Info: fmax restricted to clock pin edge rate 2.941 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 0.759 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y2_N7; Fanout = 3; REG Node = 'x[2]'
            Info: 2: + IC(0.445 ns) + CELL(0.206 ns) = 0.651 ns; Loc. = LCCOMB_X1_Y2_N18; Fanout = 1; COMB Node = 'x~17'
            Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 0.759 ns; Loc. = LCFF_X1_Y2_N19; Fanout = 1; REG Node = 'x[0]'
            Info: Total cell delay = 0.314 ns ( 41.37 % )
            Info: Total interconnect delay = 0.445 ns ( 58.63 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 2.816 ns
                Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 4; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(0.921 ns) + CELL(0.666 ns) = 2.816 ns; Loc. = LCFF_X1_Y2_N19; Fanout = 1; REG Node = 'x[0]'
                Info: Total cell delay = 1.756 ns ( 62.36 % )
                Info: Total interconnect delay = 1.060 ns ( 37.64 % )
            Info: - Longest clock path from clock "clk" to source register is 2.816 ns
                Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 4; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(0.921 ns) + CELL(0.666 ns) = 2.816 ns; Loc. = LCFF_X1_Y2_N7; Fanout = 3; REG Node = 'x[2]'
                Info: Total cell delay = 1.756 ns ( 62.36 % )
                Info: Total interconnect delay = 1.060 ns ( 37.64 % )
        Info: + Micro clock to output delay of source is 0.304 ns
        Info: + Micro setup delay of destination is -0.040 ns
Info: tsu for register "y[2]" (data pin = "clr", clock pin = "clk") is 4.327 ns
    Info: + Longest pin to register delay is 7.183 ns
        Info: 1: + IC(0.000 ns) + CELL(0.944 ns) = 0.944 ns; Loc. = PIN_42; Fanout = 4; PIN Node = 'clr'
        Info: 2: + IC(5.761 ns) + CELL(0.370 ns) = 7.075 ns; Loc. = LCCOMB_X1_Y2_N20; Fanout = 1; COMB Node = 'y~37'
        Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 7.183 ns; Loc. = LCFF_X1_Y2_N21; Fanout = 1; REG Node = 'y[2]'
        Info: Total cell delay = 1.422 ns ( 19.80 % )
        Info: Total interconnect delay = 5.761 ns ( 80.20 % )
    Info: + Micro setup delay of destination is -0.040 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.816 ns
        Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 4; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.921 ns) + CELL(0.666 ns) = 2.816 ns; Loc. = LCFF_X1_Y2_N21; Fanout = 1; REG Node = 'y[2]'
        Info: Total cell delay = 1.756 ns ( 62.36 % )
        Info: Total interconnect delay = 1.060 ns ( 37.64 % )
Info: tco from clock "clk" to destination pin "q1" through register "x[2]" is 7.306 ns
    Info: + Longest clock path from clock "clk" to source register is 2.816 ns
        Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 4; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.921 ns) + CELL(0.666 ns) = 2.816 ns; Loc. = LCFF_X1_Y2_N7; Fanout = 3; REG Node = 'x[2]'
        Info: Total cell delay = 1.756 ns ( 62.36 % )
        Info: Total interconnect delay = 1.060 ns ( 37.64 % )
    Info: + Micro clock to output delay of source is 0.304 ns
    Info: + Longest register to pin delay is 4.186 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y2_N7; Fanout = 3; REG Node = 'x[2]'
        Info: 2: + IC(0.950 ns) + CELL(3.236 ns) = 4.186 ns; Loc. = PIN_43; Fanout = 0; PIN Node = 'q1'
        Info: Total cell delay = 3.236 ns ( 77.31 % )
        Info: Total interconnect delay = 0.950 ns ( 22.69 % )
Info: th for register "x[0]" (data pin = "clr", clock pin = "clk") is -4.010 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.816 ns
        Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 4; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.921 ns) + CELL(0.666 ns) = 2.816 ns; Loc. = LCFF_X1_Y2_N19; Fanout = 1; REG Node = 'x[0]'
        Info: Total cell delay = 1.756 ns ( 62.36 % )
        Info: Total interconnect delay = 1.060 ns ( 37.64 % )
    Info: + Micro hold delay of destination is 0.306 ns
    Info: - Shortest pin to register delay is 7.132 ns
        Info: 1: + IC(0.000 ns) + CELL(0.944 ns) = 0.944 ns; Loc. = PIN_42; Fanout = 4; PIN Node = 'clr'
        Info: 2: + IC(5.761 ns) + CELL(0.319 ns) = 7.024 ns; Loc. = LCCOMB_X1_Y2_N18; Fanout = 1; COMB Node = 'x~17'
        Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 7.132 ns; Loc. = LCFF_X1_Y2_N19; Fanout = 1; REG Node = 'x[0]'
        Info: Total cell delay = 1.371 ns ( 19.22 % )
        Info: Total interconnect delay = 5.761 ns ( 80.78 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Wed Mar 21 19:52:45 2007
    Info: Elapsed time: 00:00:02