📄 d.sta.rpt
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TimeQuest Timing Analyzer report for D
Sun Apr 01 11:06:50 2007
Quartus II Version 7.0 Build 33 02/05/2007 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. TimeQuest Timing Analyzer Summary
3. SDC File List
4. Clocks
5. Fmax Summary
6. Setup Summary
7. Hold Summary
8. Minimum Pulse Width
9. Setup Transfers
10. Hold Transfers
11. Unconstrained Paths
12. TimeQuest Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+----------------------------------------------------------------------+
; TimeQuest Timing Analyzer Summary ;
+--------------------+-------------------------------------------------+
; Quartus II Version ; Version 7.0 Build 33 02/05/2007 SJ Full Version ;
; Revision Name ; D ;
; Device Family ; Cyclone II ;
; Device Name ; EP2C8T144C8 ;
; Timing Models ; Final ;
; Delay Model ; Slow Model ;
; Rise/Fall Delays ; Unavailable ;
+--------------------+-------------------------------------------------+
+---------------------------------------------------+
; SDC File List ;
+---------------+--------+--------------------------+
; SDC File Path ; Status ; Read at ;
+---------------+--------+--------------------------+
; D.sdc ; OK ; Sun Apr 01 11:06:49 2007 ;
+---------------+--------+--------------------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clocks ;
+------------+------+--------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------+
; Clock Name ; Type ; Period ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ;
+------------+------+--------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------+
; cp ; Base ; 1.000 ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { cp } ;
+------------+------+--------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------+
+-------------------------+
; Fmax Summary ;
+------------+------------+
; Fmax (MHz) ; Clock Name ;
+------------+------------+
; 629.72 ; cp ;
+------------+------------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
+--------------------------------+
; Setup Summary ;
+-------+--------+---------------+
; Clock ; Slack ; End Point TNS ;
+-------+--------+---------------+
; cp ; -0.588 ; -0.588 ;
+-------+--------+---------------+
+-------------------------------+
; Hold Summary ;
+-------+-------+---------------+
; Clock ; Slack ; End Point TNS ;
+-------+-------+---------------+
; cp ; 1.322 ; 0.000 ;
+-------+-------+---------------+
+-------------------------------------------------------------------------------------------+
; Minimum Pulse Width ;
+--------+--------------+----------------+-------+-------+------------+---------------------+
; Slack ; Actual Width ; Required Width ; Pulse ; Clock ; Clock Edge ; Target ;
+--------+--------------+----------------+-------+-------+------------+---------------------+
; -0.742 ; 0.500 ; 1.242 ; High ; cp ; Rise ; notq_temp~_emulated ;
; -0.742 ; 0.500 ; 1.242 ; Low ; cp ; Rise ; notq_temp~_emulated ;
+--------+--------------+----------------+-------+-------+------------+---------------------+
+-------------------------------------------------------------------+
; Setup Transfers ;
+------------+----------+----------+----------+----------+----------+
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+------------+----------+----------+----------+----------+----------+
; cp ; cp ; 1 ; 0 ; 0 ; 0 ;
+------------+----------+----------+----------+----------+----------+
+-------------------------------------------------------------------+
; Hold Transfers ;
+------------+----------+----------+----------+----------+----------+
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+------------+----------+----------+----------+----------+----------+
; cp ; cp ; 1 ; 0 ; 0 ; 0 ;
+------------+----------+----------+----------+----------+----------+
+------------------------------------------------+
; Unconstrained Paths ;
+---------------------------------+-------+------+
; Property ; Setup ; Hold ;
+---------------------------------+-------+------+
; Illegal Clocks ; 0 ; 0 ;
; Unconstrained Clocks ; 0 ; 0 ;
; Unconstrained Input Ports ; 3 ; 3 ;
; Unconstrained Input Port Paths ; 9 ; 9 ;
; Unconstrained Output Ports ; 2 ; 2 ;
; Unconstrained Output Port Paths ; 4 ; 4 ;
+---------------------------------+-------+------+
+------------------------------------+
; TimeQuest Timing Analyzer Messages ;
+------------------------------------+
Info: *******************************************************************
Info: Running Quartus II TimeQuest Timing Analyzer
Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
Info: Processing started: Sun Apr 01 11:06:47 2007
Info: Command: quartus_sta D -c D
Info: qsta_default_script.tcl version: 23.0.1.4
Warning: Ignored assignments for entity "fir_st" -- entity does not exist in design
Warning: Assignment of entity set_global_assignment -name DSP_BLOCK_BALANCING "LOGIC ELEMENTS" -entity fir_st is ignored
Warning: Ignored assignments for entity "lc_tdl_en" -- entity does not exist in design
Warning: Assignment of entity set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity lc_tdl_en is ignored
Warning: Ignored assignments for entity "lc_tdl_mr" -- entity does not exist in design
Warning: Assignment of entity set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity lc_tdl_mr is ignored
Warning: Ignored assignments for entity "lc_tdl_strat" -- entity does not exist in design
Warning: Assignment of entity set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity lc_tdl_strat is ignored
Warning: Ignored assignments for entity "lc_tdl_strat_cen" -- entity does not exist in design
Warning: Assignment of entity set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity lc_tdl_strat_cen is ignored
Warning: Ignored assignments for entity "mlu_nd_lc" -- entity does not exist in design
Warning: Assignment of entity set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity mlu_nd_lc is ignored
Warning: Ignored assignments for entity "msft_data" -- entity does not exist in design
Warning: Assignment of entity set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION ON -entity msft_data is ignored
Warning: Ignored assignments for entity "sadd" -- entity does not exist in design
Warning: Assignment of entity set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity sadd is ignored
Warning: Ignored assignments for entity "sadd_cen" -- entity does not exist in design
Warning: Assignment of entity set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity sadd_cen is ignored
Warning: Ignored assignments for entity "sadd_lpm" -- entity does not exist in design
Warning: Assignment of entity set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity sadd_lpm is ignored
Warning: Ignored assignments for entity "sadd_lpm_cen" -- entity does not exist in design
Warning: Assignment of entity set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity sadd_lpm_cen is ignored
Warning: Ignored assignments for entity "sadd_lpm_reg_top_cen" -- entity does not exist in design
Warning: Assignment of entity set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity sadd_lpm_reg_top_cen is ignored
Warning: Ignored assignments for entity "sadd_reg_top" -- entity does not exist in design
Warning: Assignment of entity set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity sadd_reg_top is ignored
Warning: Ignored assignments for entity "sadd_reg_top_cen" -- entity does not exist in design
Warning: Assignment of entity set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity sadd_reg_top_cen is ignored
Warning: Ignored assignments for entity "tdl_da_lc" -- entity does not exist in design
Warning: Assignment of entity set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity tdl_da_lc is ignored
Warning: Ignored assignments for entity "tsadd" -- entity does not exist in design
Warning: Assignment of entity set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity tsadd is ignored
Warning: Ignored assignments for entity "tsadd_lpm" -- entity does not exist in design
Warning: Assignment of entity set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity tsadd_lpm is ignored
Warning: Ignored assignments for entity "tsadd_lpm_cen" -- entity does not exist in design
Warning: Assignment of entity set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity tsadd_lpm_cen is ignored
Warning: Ignored assignments for entity "tsadd_lpm_reg_top_cen" -- entity does not exist in design
Warning: Assignment of entity set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity tsadd_lpm_reg_top_cen is ignored
Warning: Ignored assignments for entity "tsadd_reg_top" -- entity does not exist in design
Warning: Assignment of entity set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity tsadd_reg_top is ignored
Warning: Ignored assignments for entity "tsadd_reg_top_cen" -- entity does not exist in design
Warning: Assignment of entity set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity tsadd_reg_top_cen is ignored
Warning: Found USE_TIMEQUEST_TIMING_ANALYZER=OFF. The TimeQuest Timing Analyzer is not the default Timing Analysis Tool during full compilation.
Warning: Timing Analysis is analyzing one or more combinational loops as latches
Warning: Node "notq_temp~10|combout" is a latch
Info: Reading SDC File: 'D.sdc'
Info: No base clocks found in the design. Calling "derive_clocks -period 1.0"
Info: Deriving Clocks
Info: create_clock -period 1.000 -waveform {0.000 0.500} -name cp cp
Info: Worst-case setup slack is -0.588
Info: Slack End Point TNS Clock
Info: ========= ============= =====================
Info: -0.588 -0.588 cp
Info: Worst-case hold slack is 1.322
Info: Slack End Point TNS Clock
Info: ========= ============= =====================
Info: 1.322 0.000 cp
Info: No recovery paths to report
Info: No removal paths to report
Info: Design is not fully constrained for setup requirements
Info: Design is not fully constrained for hold requirements
Info: Quartus II TimeQuest Timing Analyzer was successful. 0 errors, 45 warnings
Info: Allocated 102 megabytes of memory during processing
Info: Processing ended: Sun Apr 01 11:06:50 2007
Info: Elapsed time: 00:00:03
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