d.map.rpt

大量VHDL写的数字系统设计有用实例达到

;     -- <=2 input functions                  ; 4     ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 7     ;
;     -- arithmetic mode                      ; 0     ;
;                                             ;       ;
; Total registers                             ; 1     ;
;     -- Dedicated logic registers            ; 1     ;
;     -- I/O registers                        ; 0     ;
;                                             ;       ;
; I/O pins                                    ; 6     ;
; Maximum fan-out node                        ; s     ;
; Maximum fan-out                             ; 5     ;
; Total fan-out                               ; 24    ;
; Average fan-out                             ; 1.71  ;
+---------------------------------------------+-------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                          ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+
; |d                         ; 7 (7)             ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 6    ; 0            ; |d                  ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+-------------------------------------------------------------+
; Registers Removed During Synthesis                          ;
+---------------------------------------+---------------------+
; Register name                         ; Reason for Removal  ;
+---------------------------------------+---------------------+
; q_temp                                ; Merged with qn_temp ;
; Total Number of Removed Registers = 1 ;                     ;
+---------------------------------------+---------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 1     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 1     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Sun May 27 20:56:31 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off D -c D
Info: Found 2 design units, including 1 entities, in source file D.vhd
    Info: Found design unit 1: d-one
    Info: Found entity 1: d
Warning: Defaulting to OpenCore or OpenCore Plus compilation for core "FIR Compiler" (6AF7_0012)
Info: Found 1 design units, including 0 entities, in source file E:/altera/70/ip/fir_compiler/lib/auk_dspip_lib_pkg.vhd
    Info: Found design unit 1: auk_dspip_lib_pkg
Info: Found 2 design units, including 0 entities, in source file E:/altera/70/ip/fir_compiler/lib/auk_dspip_math_pkg.vhd
    Info: Found design unit 1: auk_dspip_math_pkg
    Info: Found design unit 2: auk_dspip_math_pkg-body
Info: Found 2 design units, including 1 entities, in source file E:/altera/70/ip/fir_compiler/lib/auk_dspip_avalon_streaming_sink.vhd
    Info: Found design unit 1: auk_dspip_avalon_streaming_sink-rtl
    Info: Found entity 1: auk_dspip_avalon_streaming_sink
Info: Found 2 design units, including 1 entities, in source file E:/altera/70/ip/fir_compiler/lib/auk_dspip_avalon_streaming_source.vhd
    Info: Found design unit 1: auk_dspip_avalon_streaming_source-rtl
    Info: Found entity 1: auk_dspip_avalon_streaming_source
Info: Found 2 design units, including 1 entities, in source file E:/altera/70/ip/fir_compiler/lib/auk_dspip_avalon_streaming_controller.vhd
    Info: Found design unit 1: auk_dspip_avalon_streaming_controller-struct
    Info: Found entity 1: auk_dspip_avalon_streaming_controller
Warning: Can't analyze file -- file D:/my_eda/D/fir_st.v is missing
Warning: Can't analyze file -- file D:/my_eda/D/fir_new.vhd is missing
Warning: Can't analyze file -- file D:/my_eda/D/fir.vhd is missing
Info: Elaborating entity "D" for the top level hierarchy
Info: Duplicate registers merged to single register
    Info: Duplicate register "q_temp" merged to single register "qn_temp", power-up level changed
Info: Converted presettable and clearable register to equivalent circuits with latches. Registers will power-up to an undefined state, and DEVCLRn will place the registers in an undefined state.
    Info: Register "qn_temp" converted into equivalent circuit using register "qn_temp~_emulated" and latch "qn_temp~10"
Info: Implemented 13 device resources after synthesis - the final resource count might be different
    Info: Implemented 4 input pins
    Info: Implemented 2 output pins
    Info: Implemented 7 logic cells
Warning: Ignored assignments for entity "fir_st" -- entity does not exist in design
    Warning: Assignment of entity set_global_assignment -name DSP_BLOCK_BALANCING "LOGIC ELEMENTS" -entity fir_st is ignored
Warning: Ignored assignments for entity "lc_tdl_en" -- entity does not exist in design
    Warning: Assignment of entity set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity lc_tdl_en is ignored
Warning: Ignored assignments for entity "lc_tdl_mr" -- entity does not exist in design
    Warning: Assignment of entity set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity lc_tdl_mr is ignored
Warning: Ignored assignments for entity "lc_tdl_strat" -- entity does not exist in design
    Warning: Assignment of entity set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity lc_tdl_strat is ignored
Warning: Ignored assignments for entity "lc_tdl_strat_cen" -- entity does not exist in design
    Warning: Assignment of entity set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity lc_tdl_strat_cen is ignored
Warning: Ignored assignments for entity "mlu_nd_lc" -- entity does not exist in design
    Warning: Assignment of entity set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity mlu_nd_lc is ignored
Warning: Ignored assignments for entity "msft_data" -- entity does not exist in design
    Warning: Assignment of entity set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION ON -entity msft_data is ignored
Warning: Ignored assignments for entity "sadd" -- entity does not exist in design
    Warning: Assignment of entity set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity sadd is ignored
Warning: Ignored assignments for entity "sadd_cen" -- entity does not exist in design
    Warning: Assignment of entity set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity sadd_cen is ignored
Warning: Ignored assignments for entity "sadd_lpm" -- entity does not exist in design
    Warning: Assignment of entity set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity sadd_lpm is ignored
Warning: Ignored assignments for entity "sadd_lpm_cen" -- entity does not exist in design
    Warning: Assignment of entity set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity sadd_lpm_cen is ignored
Warning: Ignored assignments for entity "sadd_lpm_reg_top_cen" -- entity does not exist in design
    Warning: Assignment of entity set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity sadd_lpm_reg_top_cen is ignored
Warning: Ignored assignments for entity "sadd_reg_top" -- entity does not exist in design
    Warning: Assignment of entity set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity sadd_reg_top is ignored
Warning: Ignored assignments for entity "sadd_reg_top_cen" -- entity does not exist in design
    Warning: Assignment of entity set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity sadd_reg_top_cen is ignored
Warning: Ignored assignments for entity "tdl_da_lc" -- entity does not exist in design
    Warning: Assignment of entity set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity tdl_da_lc is ignored
Warning: Ignored assignments for entity "tsadd" -- entity does not exist in design
    Warning: Assignment of entity set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity tsadd is ignored
Warning: Ignored assignments for entity "tsadd_lpm" -- entity does not exist in design
    Warning: Assignment of entity set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity tsadd_lpm is ignored
Warning: Ignored assignments for entity "tsadd_lpm_cen" -- entity does not exist in design
    Warning: Assignment of entity set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity tsadd_lpm_cen is ignored
Warning: Ignored assignments for entity "tsadd_lpm_reg_top_cen" -- entity does not exist in design
    Warning: Assignment of entity set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity tsadd_lpm_reg_top_cen is ignored
Warning: Ignored assignments for entity "tsadd_reg_top" -- entity does not exist in design
    Warning: Assignment of entity set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity tsadd_reg_top is ignored
Warning: Ignored assignments for entity "tsadd_reg_top_cen" -- entity does not exist in design
    Warning: Assignment of entity set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity tsadd_reg_top_cen is ignored
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 46 warnings
    Info: Allocated 141 megabytes of memory during processing
    Info: Processing ended: Sun May 27 20:56:38 2007
    Info: Elapsed time: 00:00:07