d.tan.qmsg

大量VHDL写的数字系统设计有用实例达到

{ "Info" "ITDB_FULL_TPD_RESULT" "r qn 11.384 ns Longest " "Info: Longest tpd from source pin \"r\" to destination pin \"qn\" is 11.384 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.945 ns) 0.945 ns r 1 PIN PIN_31 5 " "Info: 1: + IC(0.000 ns) + CELL(0.945 ns) = 0.945 ns; Loc. = PIN_31; Fanout = 5; PIN Node = 'r'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { r } "NODE_NAME" } } { "D.vhd" "" { Text "D:/my_eda/D/D.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.762 ns) + CELL(0.370 ns) 7.077 ns qn_temp~208 2 COMB LCCOMB_X1_Y6_N18 3 " "Info: 2: + IC(5.762 ns) + CELL(0.370 ns) = 7.077 ns; Loc. = LCCOMB_X1_Y6_N18; Fanout = 3; COMB Node = 'qn_temp~208'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.132 ns" { r qn_temp~208 } "NODE_NAME" } } { "D.vhd" "" { Text "D:/my_eda/D/D.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.087 ns) + CELL(3.220 ns) 11.384 ns qn 3 PIN PIN_32 0 " "Info: 3: + IC(1.087 ns) + CELL(3.220 ns) = 11.384 ns; Loc. = PIN_32; Fanout = 0; PIN Node = 'qn'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.307 ns" { qn_temp~208 qn } "NODE_NAME" } } { "D.vhd" "" { Text "D:/my_eda/D/D.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.535 ns ( 39.84 % ) " "Info: Total cell delay = 4.535 ns ( 39.84 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.849 ns ( 60.16 % ) " "Info: Total interconnect delay = 6.849 ns ( 60.16 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "11.384 ns" { r qn_temp~208 qn } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "11.384 ns" { r r~combout qn_temp~208 qn } { 0.000ns 0.000ns 5.762ns 1.087ns } { 0.000ns 0.945ns 0.370ns 3.220ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "qn_temp~_emulated d cp 1.238 ns register " "Info: th for register \"qn_temp~_emulated\" (data pin = \"d\", clock pin = \"cp\") is 1.238 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "cp destination 3.535 ns + Longest register " "Info: + Longest clock path from clock \"cp\" to destination register is 3.535 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.934 ns) 0.934 ns cp 1 CLK PIN_141 1 " "Info: 1: + IC(0.000 ns) + CELL(0.934 ns) = 0.934 ns; Loc. = PIN_141; Fanout = 1; CLK Node = 'cp'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { cp } "NODE_NAME" } } { "D.vhd" "" { Text "D:/my_eda/D/D.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.935 ns) + CELL(0.666 ns) 3.535 ns qn_temp~_emulated 2 REG LCFF_X1_Y6_N1 1 " "Info: 2: + IC(1.935 ns) + CELL(0.666 ns) = 3.535 ns; Loc. = LCFF_X1_Y6_N1; Fanout = 1; REG Node = 'qn_temp~_emulated'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.601 ns" { cp qn_temp~_emulated } "NODE_NAME" } } { "D.vhd" "" { Text "D:/my_eda/D/D.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.600 ns ( 45.26 % ) " "Info: Total cell delay = 1.600 ns ( 45.26 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.935 ns ( 54.74 % ) " "Info: Total interconnect delay = 1.935 ns ( 54.74 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.535 ns" { cp qn_temp~_emulated } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.535 ns" { cp cp~combout qn_temp~_emulated } { 0.000ns 0.000ns 1.935ns } { 0.000ns 0.934ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" {  } { { "D.vhd" "" { Text "D:/my_eda/D/D.vhd" 13 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.603 ns - Shortest pin register " "Info: - Shortest pin to register delay is 2.603 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns d 1 PIN PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; PIN Node = 'd'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { d } "NODE_NAME" } } { "D.vhd" "" { Text "D:/my_eda/D/D.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.035 ns) + CELL(0.370 ns) 2.495 ns qn_temp~210 2 COMB LCCOMB_X1_Y6_N0 1 " "Info: 2: + IC(1.035 ns) + CELL(0.370 ns) = 2.495 ns; Loc. = LCCOMB_X1_Y6_N0; Fanout = 1; COMB Node = 'qn_temp~210'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.405 ns" { d qn_temp~210 } "NODE_NAME" } } { "D.vhd" "" { Text "D:/my_eda/D/D.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 2.603 ns qn_temp~_emulated 3 REG LCFF_X1_Y6_N1 1 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 2.603 ns; Loc. = LCFF_X1_Y6_N1; Fanout = 1; REG Node = 'qn_temp~_emulated'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { qn_temp~210 qn_temp~_emulated } "NODE_NAME" } } { "D.vhd" "" { Text "D:/my_eda/D/D.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.568 ns ( 60.24 % ) " "Info: Total cell delay = 1.568 ns ( 60.24 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.035 ns ( 39.76 % ) " "Info: Total interconnect delay = 1.035 ns ( 39.76 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.603 ns" { d qn_temp~210 qn_temp~_emulated } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.603 ns" { d d~combout qn_temp~210 qn_temp~_emulated } { 0.000ns 0.000ns 1.035ns 0.000ns } { 0.000ns 1.090ns 0.370ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.535 ns" { cp qn_temp~_emulated } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.535 ns" { cp cp~combout qn_temp~_emulated } { 0.000ns 0.000ns 1.935ns } { 0.000ns 0.934ns 0.666ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.603 ns" { d qn_temp~210 qn_temp~_emulated } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.603 ns" { d d~combout qn_temp~210 qn_temp~_emulated } { 0.000ns 0.000ns 1.035ns 0.000ns } { 0.000ns 1.090ns 0.370ns 0.108ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 3 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "103 " "Info: Allocated 103 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Sun May 27 20:57:17 2007 " "Info: Processing ended: Sun May 27 20:57:17 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}