d.tan.qmsg

大量VHDL写的数字系统设计有用实例达到

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "cp " "Info: Assuming node \"cp\" is an undefined clock" {  } { { "D.vhd" "" { Text "D:/my_eda/D/D.vhd" 5 -1 0 } } { "e:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "cp" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "cp register register qn_temp~_emulated qn_temp~_emulated 360.1 MHz Internal " "Info: Clock \"cp\" Internal fmax is restricted to 360.1 MHz between source register \"qn_temp~_emulated\" and destination register \"qn_temp~_emulated\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.777 ns " "Info: fmax restricted to clock pin edge rate 2.777 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.324 ns + Longest register register " "Info: + Longest register to register delay is 1.324 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns qn_temp~_emulated 1 REG LCFF_X1_Y6_N1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y6_N1; Fanout = 1; REG Node = 'qn_temp~_emulated'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { qn_temp~_emulated } "NODE_NAME" } } { "D.vhd" "" { Text "D:/my_eda/D/D.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.433 ns) + CELL(0.206 ns) 0.639 ns qn_temp~208 2 COMB LCCOMB_X1_Y6_N18 3 " "Info: 2: + IC(0.433 ns) + CELL(0.206 ns) = 0.639 ns; Loc. = LCCOMB_X1_Y6_N18; Fanout = 3; COMB Node = 'qn_temp~208'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.639 ns" { qn_temp~_emulated qn_temp~208 } "NODE_NAME" } } { "D.vhd" "" { Text "D:/my_eda/D/D.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.371 ns) + CELL(0.206 ns) 1.216 ns qn_temp~210 3 COMB LCCOMB_X1_Y6_N0 1 " "Info: 3: + IC(0.371 ns) + CELL(0.206 ns) = 1.216 ns; Loc. = LCCOMB_X1_Y6_N0; Fanout = 1; COMB Node = 'qn_temp~210'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.577 ns" { qn_temp~208 qn_temp~210 } "NODE_NAME" } } { "D.vhd" "" { Text "D:/my_eda/D/D.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 1.324 ns qn_temp~_emulated 4 REG LCFF_X1_Y6_N1 1 " "Info: 4: + IC(0.000 ns) + CELL(0.108 ns) = 1.324 ns; Loc. = LCFF_X1_Y6_N1; Fanout = 1; REG Node = 'qn_temp~_emulated'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { qn_temp~210 qn_temp~_emulated } "NODE_NAME" } } { "D.vhd" "" { Text "D:/my_eda/D/D.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.520 ns ( 39.27 % ) " "Info: Total cell delay = 0.520 ns ( 39.27 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.804 ns ( 60.73 % ) " "Info: Total interconnect delay = 0.804 ns ( 60.73 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.324 ns" { qn_temp~_emulated qn_temp~208 qn_temp~210 qn_temp~_emulated } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "1.324 ns" { qn_temp~_emulated qn_temp~208 qn_temp~210 qn_temp~_emulated } { 0.000ns 0.433ns 0.371ns 0.000ns } { 0.000ns 0.206ns 0.206ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "cp destination 3.535 ns + Shortest register " "Info: + Shortest clock path from clock \"cp\" to destination register is 3.535 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.934 ns) 0.934 ns cp 1 CLK PIN_141 1 " "Info: 1: + IC(0.000 ns) + CELL(0.934 ns) = 0.934 ns; Loc. = PIN_141; Fanout = 1; CLK Node = 'cp'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { cp } "NODE_NAME" } } { "D.vhd" "" { Text "D:/my_eda/D/D.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.935 ns) + CELL(0.666 ns) 3.535 ns qn_temp~_emulated 2 REG LCFF_X1_Y6_N1 1 " "Info: 2: + IC(1.935 ns) + CELL(0.666 ns) = 3.535 ns; Loc. = LCFF_X1_Y6_N1; Fanout = 1; REG Node = 'qn_temp~_emulated'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.601 ns" { cp qn_temp~_emulated } "NODE_NAME" } } { "D.vhd" "" { Text "D:/my_eda/D/D.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.600 ns ( 45.26 % ) " "Info: Total cell delay = 1.600 ns ( 45.26 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.935 ns ( 54.74 % ) " "Info: Total interconnect delay = 1.935 ns ( 54.74 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.535 ns" { cp qn_temp~_emulated } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.535 ns" { cp cp~combout qn_temp~_emulated } { 0.000ns 0.000ns 1.935ns } { 0.000ns 0.934ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "cp source 3.535 ns - Longest register " "Info: - Longest clock path from clock \"cp\" to source register is 3.535 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.934 ns) 0.934 ns cp 1 CLK PIN_141 1 " "Info: 1: + IC(0.000 ns) + CELL(0.934 ns) = 0.934 ns; Loc. = PIN_141; Fanout = 1; CLK Node = 'cp'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { cp } "NODE_NAME" } } { "D.vhd" "" { Text "D:/my_eda/D/D.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.935 ns) + CELL(0.666 ns) 3.535 ns qn_temp~_emulated 2 REG LCFF_X1_Y6_N1 1 " "Info: 2: + IC(1.935 ns) + CELL(0.666 ns) = 3.535 ns; Loc. = LCFF_X1_Y6_N1; Fanout = 1; REG Node = 'qn_temp~_emulated'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.601 ns" { cp qn_temp~_emulated } "NODE_NAME" } } { "D.vhd" "" { Text "D:/my_eda/D/D.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.600 ns ( 45.26 % ) " "Info: Total cell delay = 1.600 ns ( 45.26 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.935 ns ( 54.74 % ) " "Info: Total interconnect delay = 1.935 ns ( 54.74 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.535 ns" { cp qn_temp~_emulated } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.535 ns" { cp cp~combout qn_temp~_emulated } { 0.000ns 0.000ns 1.935ns } { 0.000ns 0.934ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.535 ns" { cp qn_temp~_emulated } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.535 ns" { cp cp~combout qn_temp~_emulated } { 0.000ns 0.000ns 1.935ns } { 0.000ns 0.934ns 0.666ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.535 ns" { cp qn_temp~_emulated } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.535 ns" { cp cp~combout qn_temp~_emulated } { 0.000ns 0.000ns 1.935ns } { 0.000ns 0.934ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "D.vhd" "" { Text "D:/my_eda/D/D.vhd" 13 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "D.vhd" "" { Text "D:/my_eda/D/D.vhd" 13 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.324 ns" { qn_temp~_emulated qn_temp~208 qn_temp~210 qn_temp~_emulated } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "1.324 ns" { qn_temp~_emulated qn_temp~208 qn_temp~210 qn_temp~_emulated } { 0.000ns 0.433ns 0.371ns 0.000ns } { 0.000ns 0.206ns 0.206ns 0.108ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.535 ns" { cp qn_temp~_emulated } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.535 ns" { cp cp~combout qn_temp~_emulated } { 0.000ns 0.000ns 1.935ns } { 0.000ns 0.934ns 0.666ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.535 ns" { cp qn_temp~_emulated } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.535 ns" { cp cp~combout qn_temp~_emulated } { 0.000ns 0.000ns 1.935ns } { 0.000ns 0.934ns 0.666ns } "" } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { qn_temp~_emulated } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { qn_temp~_emulated } {  } {  } "" } } { "D.vhd" "" { Text "D:/my_eda/D/D.vhd" 13 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_TSU_RESULT" "qn_temp~_emulated r cp 4.602 ns register " "Info: tsu for register \"qn_temp~_emulated\" (data pin = \"r\", clock pin = \"cp\") is 4.602 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.177 ns + Longest pin register " "Info: + Longest pin to register delay is 8.177 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.945 ns) 0.945 ns r 1 PIN PIN_31 5 " "Info: 1: + IC(0.000 ns) + CELL(0.945 ns) = 0.945 ns; Loc. = PIN_31; Fanout = 5; PIN Node = 'r'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { r } "NODE_NAME" } } { "D.vhd" "" { Text "D:/my_eda/D/D.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.761 ns) + CELL(0.370 ns) 7.076 ns qn_temp~209 2 COMB LCCOMB_X1_Y6_N22 1 " "Info: 2: + IC(5.761 ns) + CELL(0.370 ns) = 7.076 ns; Loc. = LCCOMB_X1_Y6_N22; Fanout = 1; COMB Node = 'qn_temp~209'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.131 ns" { r qn_temp~209 } "NODE_NAME" } } { "D.vhd" "" { Text "D:/my_eda/D/D.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.369 ns) + CELL(0.624 ns) 8.069 ns qn_temp~210 3 COMB LCCOMB_X1_Y6_N0 1 " "Info: 3: + IC(0.369 ns) + CELL(0.624 ns) = 8.069 ns; Loc. = LCCOMB_X1_Y6_N0; Fanout = 1; COMB Node = 'qn_temp~210'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.993 ns" { qn_temp~209 qn_temp~210 } "NODE_NAME" } } { "D.vhd" "" { Text "D:/my_eda/D/D.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 8.177 ns qn_temp~_emulated 4 REG LCFF_X1_Y6_N1 1 " "Info: 4: + IC(0.000 ns) + CELL(0.108 ns) = 8.177 ns; Loc. = LCFF_X1_Y6_N1; Fanout = 1; REG Node = 'qn_temp~_emulated'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { qn_temp~210 qn_temp~_emulated } "NODE_NAME" } } { "D.vhd" "" { Text "D:/my_eda/D/D.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.047 ns ( 25.03 % ) " "Info: Total cell delay = 2.047 ns ( 25.03 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.130 ns ( 74.97 % ) " "Info: Total interconnect delay = 6.130 ns ( 74.97 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.177 ns" { r qn_temp~209 qn_temp~210 qn_temp~_emulated } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "8.177 ns" { r r~combout qn_temp~209 qn_temp~210 qn_temp~_emulated } { 0.000ns 0.000ns 5.761ns 0.369ns 0.000ns } { 0.000ns 0.945ns 0.370ns 0.624ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "D.vhd" "" { Text "D:/my_eda/D/D.vhd" 13 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "cp destination 3.535 ns - Shortest register " "Info: - Shortest clock path from clock \"cp\" to destination register is 3.535 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.934 ns) 0.934 ns cp 1 CLK PIN_141 1 " "Info: 1: + IC(0.000 ns) + CELL(0.934 ns) = 0.934 ns; Loc. = PIN_141; Fanout = 1; CLK Node = 'cp'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { cp } "NODE_NAME" } } { "D.vhd" "" { Text "D:/my_eda/D/D.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.935 ns) + CELL(0.666 ns) 3.535 ns qn_temp~_emulated 2 REG LCFF_X1_Y6_N1 1 " "Info: 2: + IC(1.935 ns) + CELL(0.666 ns) = 3.535 ns; Loc. = LCFF_X1_Y6_N1; Fanout = 1; REG Node = 'qn_temp~_emulated'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.601 ns" { cp qn_temp~_emulated } "NODE_NAME" } } { "D.vhd" "" { Text "D:/my_eda/D/D.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.600 ns ( 45.26 % ) " "Info: Total cell delay = 1.600 ns ( 45.26 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.935 ns ( 54.74 % ) " "Info: Total interconnect delay = 1.935 ns ( 54.74 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.535 ns" { cp qn_temp~_emulated } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.535 ns" { cp cp~combout qn_temp~_emulated } { 0.000ns 0.000ns 1.935ns } { 0.000ns 0.934ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.177 ns" { r qn_temp~209 qn_temp~210 qn_temp~_emulated } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "8.177 ns" { r r~combout qn_temp~209 qn_temp~210 qn_temp~_emulated } { 0.000ns 0.000ns 5.761ns 0.369ns 0.000ns } { 0.000ns 0.945ns 0.370ns 0.624ns 0.108ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.535 ns" { cp qn_temp~_emulated } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.535 ns" { cp cp~combout qn_temp~_emulated } { 0.000ns 0.000ns 1.935ns } { 0.000ns 0.934ns 0.666ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "cp qn qn_temp~_emulated 8.785 ns register " "Info: tco from clock \"cp\" to destination pin \"qn\" through register \"qn_temp~_emulated\" is 8.785 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "cp source 3.535 ns + Longest register " "Info: + Longest clock path from clock \"cp\" to source register is 3.535 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.934 ns) 0.934 ns cp 1 CLK PIN_141 1 " "Info: 1: + IC(0.000 ns) + CELL(0.934 ns) = 0.934 ns; Loc. = PIN_141; Fanout = 1; CLK Node = 'cp'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { cp } "NODE_NAME" } } { "D.vhd" "" { Text "D:/my_eda/D/D.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.935 ns) + CELL(0.666 ns) 3.535 ns qn_temp~_emulated 2 REG LCFF_X1_Y6_N1 1 " "Info: 2: + IC(1.935 ns) + CELL(0.666 ns) = 3.535 ns; Loc. = LCFF_X1_Y6_N1; Fanout = 1; REG Node = 'qn_temp~_emulated'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.601 ns" { cp qn_temp~_emulated } "NODE_NAME" } } { "D.vhd" "" { Text "D:/my_eda/D/D.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.600 ns ( 45.26 % ) " "Info: Total cell delay = 1.600 ns ( 45.26 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.935 ns ( 54.74 % ) " "Info: Total interconnect delay = 1.935 ns ( 54.74 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.535 ns" { cp qn_temp~_emulated } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.535 ns" { cp cp~combout qn_temp~_emulated } { 0.000ns 0.000ns 1.935ns } { 0.000ns 0.934ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "D.vhd" "" { Text "D:/my_eda/D/D.vhd" 13 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.946 ns + Longest register pin " "Info: + Longest register to pin delay is 4.946 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns qn_temp~_emulated 1 REG LCFF_X1_Y6_N1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y6_N1; Fanout = 1; REG Node = 'qn_temp~_emulated'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { qn_temp~_emulated } "NODE_NAME" } } { "D.vhd" "" { Text "D:/my_eda/D/D.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.433 ns) + CELL(0.206 ns) 0.639 ns qn_temp~208 2 COMB LCCOMB_X1_Y6_N18 3 " "Info: 2: + IC(0.433 ns) + CELL(0.206 ns) = 0.639 ns; Loc. = LCCOMB_X1_Y6_N18; Fanout = 3; COMB Node = 'qn_temp~208'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.639 ns" { qn_temp~_emulated qn_temp~208 } "NODE_NAME" } } { "D.vhd" "" { Text "D:/my_eda/D/D.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.087 ns) + CELL(3.220 ns) 4.946 ns qn 3 PIN PIN_32 0 " "Info: 3: + IC(1.087 ns) + CELL(3.220 ns) = 4.946 ns; Loc. = PIN_32; Fanout = 0; PIN Node = 'qn'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.307 ns" { qn_temp~208 qn } "NODE_NAME" } } { "D.vhd" "" { Text "D:/my_eda/D/D.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.426 ns ( 69.27 % ) " "Info: Total cell delay = 3.426 ns ( 69.27 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.520 ns ( 30.73 % ) " "Info: Total interconnect delay = 1.520 ns ( 30.73 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.946 ns" { qn_temp~_emulated qn_temp~208 qn } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "4.946 ns" { qn_temp~_emulated qn_temp~208 qn } { 0.000ns 0.433ns 1.087ns } { 0.000ns 0.206ns 3.220ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.535 ns" { cp qn_temp~_emulated } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.535 ns" { cp cp~combout qn_temp~_emulated } { 0.000ns 0.000ns 1.935ns } { 0.000ns 0.934ns 0.666ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.946 ns" { qn_temp~_emulated qn_temp~208 qn } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "4.946 ns" { qn_temp~_emulated qn_temp~208 qn } { 0.000ns 0.433ns 1.087ns } { 0.000ns 0.206ns 3.220ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}