d.fnsim.qmsg

大量VHDL写的数字系统设计有用实例达到

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Functional Simulation Netlist Generation Quartus II " "Info: Running Quartus II Functional Simulation Netlist Generation" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.0 Build 33 02/05/2007 SJ Full Version " "Info: Version 7.0 Build 33 02/05/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun May 27 20:58:47 2007 " "Info: Processing started: Sun May 27 20:58:47 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off D -c D --generate_functional_sim_netlist " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off D -c D --generate_functional_sim_netlist" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "D.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file D.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 d-one " "Info: Found design unit 1: d-one" {  } { { "D.vhd" "" { Text "D:/my_eda/D/D.vhd" 8 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 d " "Info: Found entity 1: d" {  } { { "D.vhd" "" { Text "D:/my_eda/D/D.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Warning" "WCPT_DEFAULTING_TO_OPENCORE" "\"FIR Compiler\" (6AF7_0012) " "Warning: Defaulting to OpenCore or OpenCore Plus compilation for core \"FIR Compiler\" (6AF7_0012)" {  } {  } 0 0 "Defaulting to OpenCore or OpenCore Plus compilation for core %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "E:/altera/70/ip/fir_compiler/lib/auk_dspip_lib_pkg.vhd 1 0 " "Info: Found 1 design units, including 0 entities, in source file E:/altera/70/ip/fir_compiler/lib/auk_dspip_lib_pkg.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_lib_pkg " "Info: Found design unit 1: auk_dspip_lib_pkg" {  } { { "E:/altera/70/ip/fir_compiler/lib/auk_dspip_lib_pkg.vhd" "" { Text "E:/altera/70/ip/fir_compiler/lib/auk_dspip_lib_pkg.vhd" 13 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "E:/altera/70/ip/fir_compiler/lib/auk_dspip_math_pkg.vhd 2 0 " "Info: Found 2 design units, including 0 entities, in source file E:/altera/70/ip/fir_compiler/lib/auk_dspip_math_pkg.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_math_pkg " "Info: Found design unit 1: auk_dspip_math_pkg" {  } { { "E:/altera/70/ip/fir_compiler/lib/auk_dspip_math_pkg.vhd" "" { Text "E:/altera/70/ip/fir_compiler/lib/auk_dspip_math_pkg.vhd" 41 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 auk_dspip_math_pkg-body " "Info: Found design unit 2: auk_dspip_math_pkg-body" {  } { { "E:/altera/70/ip/fir_compiler/lib/auk_dspip_math_pkg.vhd" "" { Text "E:/altera/70/ip/fir_compiler/lib/auk_dspip_math_pkg.vhd" 118 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "E:/altera/70/ip/fir_compiler/lib/auk_dspip_avalon_streaming_sink.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file E:/altera/70/ip/fir_compiler/lib/auk_dspip_avalon_streaming_sink.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_avalon_streaming_sink-rtl " "Info: Found design unit 1: auk_dspip_avalon_streaming_sink-rtl" {  } { { "E:/altera/70/ip/fir_compiler/lib/auk_dspip_avalon_streaming_sink.vhd" "" { Text "E:/altera/70/ip/fir_compiler/lib/auk_dspip_avalon_streaming_sink.vhd" 93 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 auk_dspip_avalon_streaming_sink " "Info: Found entity 1: auk_dspip_avalon_streaming_sink" {  } { { "E:/altera/70/ip/fir_compiler/lib/auk_dspip_avalon_streaming_sink.vhd" "" { Text "E:/altera/70/ip/fir_compiler/lib/auk_dspip_avalon_streaming_sink.vhd" 47 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "E:/altera/70/ip/fir_compiler/lib/auk_dspip_avalon_streaming_source.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file E:/altera/70/ip/fir_compiler/lib/auk_dspip_avalon_streaming_source.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_avalon_streaming_source-rtl " "Info: Found design unit 1: auk_dspip_avalon_streaming_source-rtl" {  } { { "E:/altera/70/ip/fir_compiler/lib/auk_dspip_avalon_streaming_source.vhd" "" { Text "E:/altera/70/ip/fir_compiler/lib/auk_dspip_avalon_streaming_source.vhd" 92 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 auk_dspip_avalon_streaming_source " "Info: Found entity 1: auk_dspip_avalon_streaming_source" {  } { { "E:/altera/70/ip/fir_compiler/lib/auk_dspip_avalon_streaming_source.vhd" "" { Text "E:/altera/70/ip/fir_compiler/lib/auk_dspip_avalon_streaming_source.vhd" 59 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "E:/altera/70/ip/fir_compiler/lib/auk_dspip_avalon_streaming_controller.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file E:/altera/70/ip/fir_compiler/lib/auk_dspip_avalon_streaming_controller.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_avalon_streaming_controller-struct " "Info: Found design unit 1: auk_dspip_avalon_streaming_controller-struct" {  } { { "E:/altera/70/ip/fir_compiler/lib/auk_dspip_avalon_streaming_controller.vhd" "" { Text "E:/altera/70/ip/fir_compiler/lib/auk_dspip_avalon_streaming_controller.vhd" 66 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 auk_dspip_avalon_streaming_controller " "Info: Found entity 1: auk_dspip_avalon_streaming_controller" {  } { { "E:/altera/70/ip/fir_compiler/lib/auk_dspip_avalon_streaming_controller.vhd" "" { Text "E:/altera/70/ip/fir_compiler/lib/auk_dspip_avalon_streaming_controller.vhd" 42 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "D:/my_eda/D/fir_st.v " "Warning: Can't analyze file -- file D:/my_eda/D/fir_st.v is missing" {  } {  } 0 0 "Can't analyze file -- file %1!s! is missing" 0 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "D:/my_eda/D/fir_new.vhd " "Warning: Can't analyze file -- file D:/my_eda/D/fir_new.vhd is missing" {  } {  } 0 0 "Can't analyze file -- file %1!s! is missing" 0 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "D:/my_eda/D/fir.vhd " "Warning: Can't analyze file -- file D:/my_eda/D/fir.vhd is missing" {  } {  } 0 0 "Can't analyze file -- file %1!s! is missing" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "D " "Info: Elaborating entity \"D\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WQCU_FOUND_UNUSABLE_ASSIGNMENTS_FOR_ENTITY" "fir_st " "Warning: Ignored assignments for entity \"fir_st\" -- entity does not exist in design" { { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name DSP_BLOCK_BALANCING \"LOGIC ELEMENTS\" -entity fir_st " "Warning: Assignment of entity set_global_assignment -name DSP_BLOCK_BALANCING \"LOGIC ELEMENTS\" -entity fir_st is ignored" {  } {  } 0 0 "Assignment of entity %1!s! is ignored" 0 0}  } {  } 0 0 "Ignored assignments for entity \"%1!s!\" -- entity does not exist in design" 0 0}
{ "Warning" "WQCU_FOUND_UNUSABLE_ASSIGNMENTS_FOR_ENTITY" "lc_tdl_en " "Warning: Ignored assignments for entity \"lc_tdl_en\" -- entity does not exist in design" { { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity lc_tdl_en " "Warning: Assignment of entity set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity lc_tdl_en is ignored" {  } {  } 0 0 "Assignment of entity %1!s! is ignored" 0 0}  } {  } 0 0 "Ignored assignments for entity \"%1!s!\" -- entity does not exist in design" 0 0}
{ "Warning" "WQCU_FOUND_UNUSABLE_ASSIGNMENTS_FOR_ENTITY" "lc_tdl_mr " "Warning: Ignored assignments for entity \"lc_tdl_mr\" -- entity does not exist in design" { { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity lc_tdl_mr " "Warning: Assignment of entity set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity lc_tdl_mr is ignored" {  } {  } 0 0 "Assignment of entity %1!s! is ignored" 0 0}  } {  } 0 0 "Ignored assignments for entity \"%1!s!\" -- entity does not exist in design" 0 0}
{ "Warning" "WQCU_FOUND_UNUSABLE_ASSIGNMENTS_FOR_ENTITY" "lc_tdl_strat " "Warning: Ignored assignments for entity \"lc_tdl_strat\" -- entity does not exist in design" { { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity lc_tdl_strat " "Warning: Assignment of entity set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity lc_tdl_strat is ignored" {  } {  } 0 0 "Assignment of entity %1!s! is ignored" 0 0}  } {  } 0 0 "Ignored assignments for entity \"%1!s!\" -- entity does not exist in design" 0 0}
{ "Warning" "WQCU_FOUND_UNUSABLE_ASSIGNMENTS_FOR_ENTITY" "lc_tdl_strat_cen " "Warning: Ignored assignments for entity \"lc_tdl_strat_cen\" -- entity does not exist in design" { { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity lc_tdl_strat_cen " "Warning: Assignment of entity set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity lc_tdl_strat_cen is ignored" {  } {  } 0 0 "Assignment of entity %1!s! is ignored" 0 0}  } {  } 0 0 "Ignored assignments for entity \"%1!s!\" -- entity does not exist in design" 0 0}