d.sta.qmsg

大量VHDL写的数字系统设计有用实例达到

{ "Warning" "WQCU_FOUND_UNUSABLE_ASSIGNMENTS_FOR_ENTITY" "tsadd " "Warning: Ignored assignments for entity \"tsadd\" -- entity does not exist in design" { { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity tsadd " "Warning: Assignment of entity set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity tsadd is ignored" {  } {  } 0 0 "Assignment of entity %1!s! is ignored" 0 0}  } {  } 0 0 "Ignored assignments for entity \"%1!s!\" -- entity does not exist in design" 0 0}
{ "Warning" "WQCU_FOUND_UNUSABLE_ASSIGNMENTS_FOR_ENTITY" "tsadd_lpm " "Warning: Ignored assignments for entity \"tsadd_lpm\" -- entity does not exist in design" { { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity tsadd_lpm " "Warning: Assignment of entity set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity tsadd_lpm is ignored" {  } {  } 0 0 "Assignment of entity %1!s! is ignored" 0 0}  } {  } 0 0 "Ignored assignments for entity \"%1!s!\" -- entity does not exist in design" 0 0}
{ "Warning" "WQCU_FOUND_UNUSABLE_ASSIGNMENTS_FOR_ENTITY" "tsadd_lpm_cen " "Warning: Ignored assignments for entity \"tsadd_lpm_cen\" -- entity does not exist in design" { { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity tsadd_lpm_cen " "Warning: Assignment of entity set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity tsadd_lpm_cen is ignored" {  } {  } 0 0 "Assignment of entity %1!s! is ignored" 0 0}  } {  } 0 0 "Ignored assignments for entity \"%1!s!\" -- entity does not exist in design" 0 0}
{ "Warning" "WQCU_FOUND_UNUSABLE_ASSIGNMENTS_FOR_ENTITY" "tsadd_lpm_reg_top_cen " "Warning: Ignored assignments for entity \"tsadd_lpm_reg_top_cen\" -- entity does not exist in design" { { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity tsadd_lpm_reg_top_cen " "Warning: Assignment of entity set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity tsadd_lpm_reg_top_cen is ignored" {  } {  } 0 0 "Assignment of entity %1!s! is ignored" 0 0}  } {  } 0 0 "Ignored assignments for entity \"%1!s!\" -- entity does not exist in design" 0 0}
{ "Warning" "WQCU_FOUND_UNUSABLE_ASSIGNMENTS_FOR_ENTITY" "tsadd_reg_top " "Warning: Ignored assignments for entity \"tsadd_reg_top\" -- entity does not exist in design" { { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity tsadd_reg_top " "Warning: Assignment of entity set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity tsadd_reg_top is ignored" {  } {  } 0 0 "Assignment of entity %1!s! is ignored" 0 0}  } {  } 0 0 "Ignored assignments for entity \"%1!s!\" -- entity does not exist in design" 0 0}
{ "Warning" "WQCU_FOUND_UNUSABLE_ASSIGNMENTS_FOR_ENTITY" "tsadd_reg_top_cen " "Warning: Ignored assignments for entity \"tsadd_reg_top_cen\" -- entity does not exist in design" { { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity tsadd_reg_top_cen " "Warning: Assignment of entity set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity tsadd_reg_top_cen is ignored" {  } {  } 0 0 "Assignment of entity %1!s! is ignored" 0 0}  } {  } 0 0 "Ignored assignments for entity \"%1!s!\" -- entity does not exist in design" 0 0}
{ "Warning" "WSTA_NOT_IN_STA_MODE" "" "Warning: Found USE_TIMEQUEST_TIMING_ANALYZER=OFF. The TimeQuest Timing Analyzer is not the default Timing Analysis Tool during full compilation." {  } {  } 0 0 "Found USE_TIMEQUEST_TIMING_ANALYZER=OFF. The TimeQuest Timing Analyzer is not the default Timing Analysis Tool during full compilation." 0 0}
{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "" "Warning: Timing Analysis is analyzing one or more combinational loops as latches" { { "Warning" "WTDB_COMB_LATCH_NODE" "notq_temp~10\|combout " "Warning: Node \"notq_temp~10\|combout\" is a latch" {  } { { "D.vhd" "" { Text "D:/my_eda/D/D.vhd" 13 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0}  } {  } 0 0 "Timing Analysis is analyzing one or more combinational loops as latches" 0 0}
{ "Info" "ISTA_SDC_FOUND" "D.sdc " "Info: Reading SDC File: 'D.sdc'" {  } {  } 0 0 "Reading SDC File: '%1!s!'" 0 0}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "Info: No base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 0 "No %1!s! found in the design. Calling %2!s!" 0 0}
{ "Info" "ISTA_GENERIC_INFO" "Deriving Clocks " "Info: Deriving Clocks" { { "Info" "ISTA_GENERIC_INFO" "create_clock -period 1.000 -waveform \{0.000 0.500\} -name cp cp " "Info: create_clock -period 1.000 -waveform \{0.000 0.500\} -name cp cp" {  } {  } 0 0 "%1!s!" 0 0}  } {  } 0 0 "%1!s!" 0 0}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -0.588 " "Info: Worst-case setup slack is -0.588" { { "Info" "ISTA_GENERIC_INFO" "    Slack End Point TNS Clock  " "Info:     Slack End Point TNS Clock " {  } {  } 0 0 "%1!s!" 0 0} { "Info" "ISTA_GENERIC_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "ISTA_GENERIC_INFO" "   -0.588        -0.588 cp  " "Info:    -0.588        -0.588 cp " {  } {  } 0 0 "%1!s!" 0 0}  } {  } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 1.322 " "Info: Worst-case hold slack is 1.322" { { "Info" "ISTA_GENERIC_INFO" "    Slack End Point TNS Clock  " "Info:     Slack End Point TNS Clock " {  } {  } 0 0 "%1!s!" 0 0} { "Info" "ISTA_GENERIC_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "ISTA_GENERIC_INFO" "    1.322         0.000 cp  " "Info:     1.322         0.000 cp " {  } {  } 0 0 "%1!s!" 0 0}  } {  } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "recovery " "Info: No recovery paths to report" {  } {  } 0 0 "No %1!s! paths to report" 0 0}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "removal " "Info: No removal paths to report" {  } {  } 0 0 "No %1!s! paths to report" 0 0}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Info: Design is not fully constrained for setup requirements" {  } {  } 0 0 "Design is not fully constrained for %1!s! requirements" 0 0}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Info: Design is not fully constrained for hold requirements" {  } {  } 0 0 "Design is not fully constrained for %1!s! requirements" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 45 s Quartus II " "Info: Quartus II TimeQuest Timing Analyzer was successful. 0 errors, 45 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "102 " "Info: Allocated 102 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 01 11:06:50 2007 " "Info: Processing ended: Sun Apr 01 11:06:50 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}