d.tan.rpt

大量VHDL写的数字系统设计有用实例达到

; N/A   ; None         ; 8.613 ns   ; qn_temp~_emulated ; q  ; cp         ;
+-------+--------------+------------+-------------------+----+------------+


+---------------------------------------------------------+
; tpd                                                     ;
+-------+-------------------+-----------------+------+----+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+------+----+
; N/A   ; None              ; 11.384 ns       ; r    ; qn ;
; N/A   ; None              ; 11.238 ns       ; s    ; qn ;
; N/A   ; None              ; 11.212 ns       ; r    ; q  ;
; N/A   ; None              ; 11.066 ns       ; s    ; q  ;
+-------+-------------------+-----------------+------+----+


+-------------------------------------------------------------------------------+
; th                                                                            ;
+---------------+-------------+-----------+------+-------------------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To                ; To Clock ;
+---------------+-------------+-----------+------+-------------------+----------+
; N/A           ; None        ; 1.238 ns  ; d    ; qn_temp~_emulated ; cp       ;
; N/A           ; None        ; -3.710 ns ; s    ; qn_temp~_emulated ; cp       ;
; N/A           ; None        ; -3.921 ns ; r    ; qn_temp~_emulated ; cp       ;
+---------------+-------------+-----------+------+-------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Sun May 27 20:57:15 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off D -c D --timing_analysis_only
Warning: Timing Analysis is analyzing one or more combinational loops as latches
    Warning: Node "qn_temp~10" is a latch
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "cp" is an undefined clock
Info: Clock "cp" Internal fmax is restricted to 360.1 MHz between source register "qn_temp~_emulated" and destination register "qn_temp~_emulated"
    Info: fmax restricted to clock pin edge rate 2.777 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.324 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y6_N1; Fanout = 1; REG Node = 'qn_temp~_emulated'
            Info: 2: + IC(0.433 ns) + CELL(0.206 ns) = 0.639 ns; Loc. = LCCOMB_X1_Y6_N18; Fanout = 3; COMB Node = 'qn_temp~208'
            Info: 3: + IC(0.371 ns) + CELL(0.206 ns) = 1.216 ns; Loc. = LCCOMB_X1_Y6_N0; Fanout = 1; COMB Node = 'qn_temp~210'
            Info: 4: + IC(0.000 ns) + CELL(0.108 ns) = 1.324 ns; Loc. = LCFF_X1_Y6_N1; Fanout = 1; REG Node = 'qn_temp~_emulated'
            Info: Total cell delay = 0.520 ns ( 39.27 % )
            Info: Total interconnect delay = 0.804 ns ( 60.73 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "cp" to destination register is 3.535 ns
                Info: 1: + IC(0.000 ns) + CELL(0.934 ns) = 0.934 ns; Loc. = PIN_141; Fanout = 1; CLK Node = 'cp'
                Info: 2: + IC(1.935 ns) + CELL(0.666 ns) = 3.535 ns; Loc. = LCFF_X1_Y6_N1; Fanout = 1; REG Node = 'qn_temp~_emulated'
                Info: Total cell delay = 1.600 ns ( 45.26 % )
                Info: Total interconnect delay = 1.935 ns ( 54.74 % )
            Info: - Longest clock path from clock "cp" to source register is 3.535 ns
                Info: 1: + IC(0.000 ns) + CELL(0.934 ns) = 0.934 ns; Loc. = PIN_141; Fanout = 1; CLK Node = 'cp'
                Info: 2: + IC(1.935 ns) + CELL(0.666 ns) = 3.535 ns; Loc. = LCFF_X1_Y6_N1; Fanout = 1; REG Node = 'qn_temp~_emulated'
                Info: Total cell delay = 1.600 ns ( 45.26 % )
                Info: Total interconnect delay = 1.935 ns ( 54.74 % )
        Info: + Micro clock to output delay of source is 0.304 ns
        Info: + Micro setup delay of destination is -0.040 ns
Info: tsu for register "qn_temp~_emulated" (data pin = "r", clock pin = "cp") is 4.602 ns
    Info: + Longest pin to register delay is 8.177 ns
        Info: 1: + IC(0.000 ns) + CELL(0.945 ns) = 0.945 ns; Loc. = PIN_31; Fanout = 5; PIN Node = 'r'
        Info: 2: + IC(5.761 ns) + CELL(0.370 ns) = 7.076 ns; Loc. = LCCOMB_X1_Y6_N22; Fanout = 1; COMB Node = 'qn_temp~209'
        Info: 3: + IC(0.369 ns) + CELL(0.624 ns) = 8.069 ns; Loc. = LCCOMB_X1_Y6_N0; Fanout = 1; COMB Node = 'qn_temp~210'
        Info: 4: + IC(0.000 ns) + CELL(0.108 ns) = 8.177 ns; Loc. = LCFF_X1_Y6_N1; Fanout = 1; REG Node = 'qn_temp~_emulated'
        Info: Total cell delay = 2.047 ns ( 25.03 % )
        Info: Total interconnect delay = 6.130 ns ( 74.97 % )
    Info: + Micro setup delay of destination is -0.040 ns
    Info: - Shortest clock path from clock "cp" to destination register is 3.535 ns
        Info: 1: + IC(0.000 ns) + CELL(0.934 ns) = 0.934 ns; Loc. = PIN_141; Fanout = 1; CLK Node = 'cp'
        Info: 2: + IC(1.935 ns) + CELL(0.666 ns) = 3.535 ns; Loc. = LCFF_X1_Y6_N1; Fanout = 1; REG Node = 'qn_temp~_emulated'
        Info: Total cell delay = 1.600 ns ( 45.26 % )
        Info: Total interconnect delay = 1.935 ns ( 54.74 % )
Info: tco from clock "cp" to destination pin "qn" through register "qn_temp~_emulated" is 8.785 ns
    Info: + Longest clock path from clock "cp" to source register is 3.535 ns
        Info: 1: + IC(0.000 ns) + CELL(0.934 ns) = 0.934 ns; Loc. = PIN_141; Fanout = 1; CLK Node = 'cp'
        Info: 2: + IC(1.935 ns) + CELL(0.666 ns) = 3.535 ns; Loc. = LCFF_X1_Y6_N1; Fanout = 1; REG Node = 'qn_temp~_emulated'
        Info: Total cell delay = 1.600 ns ( 45.26 % )
        Info: Total interconnect delay = 1.935 ns ( 54.74 % )
    Info: + Micro clock to output delay of source is 0.304 ns
    Info: + Longest register to pin delay is 4.946 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y6_N1; Fanout = 1; REG Node = 'qn_temp~_emulated'
        Info: 2: + IC(0.433 ns) + CELL(0.206 ns) = 0.639 ns; Loc. = LCCOMB_X1_Y6_N18; Fanout = 3; COMB Node = 'qn_temp~208'
        Info: 3: + IC(1.087 ns) + CELL(3.220 ns) = 4.946 ns; Loc. = PIN_32; Fanout = 0; PIN Node = 'qn'
        Info: Total cell delay = 3.426 ns ( 69.27 % )
        Info: Total interconnect delay = 1.520 ns ( 30.73 % )
Info: Longest tpd from source pin "r" to destination pin "qn" is 11.384 ns
    Info: 1: + IC(0.000 ns) + CELL(0.945 ns) = 0.945 ns; Loc. = PIN_31; Fanout = 5; PIN Node = 'r'
    Info: 2: + IC(5.762 ns) + CELL(0.370 ns) = 7.077 ns; Loc. = LCCOMB_X1_Y6_N18; Fanout = 3; COMB Node = 'qn_temp~208'
    Info: 3: + IC(1.087 ns) + CELL(3.220 ns) = 11.384 ns; Loc. = PIN_32; Fanout = 0; PIN Node = 'qn'
    Info: Total cell delay = 4.535 ns ( 39.84 % )
    Info: Total interconnect delay = 6.849 ns ( 60.16 % )
Info: th for register "qn_temp~_emulated" (data pin = "d", clock pin = "cp") is 1.238 ns
    Info: + Longest clock path from clock "cp" to destination register is 3.535 ns
        Info: 1: + IC(0.000 ns) + CELL(0.934 ns) = 0.934 ns; Loc. = PIN_141; Fanout = 1; CLK Node = 'cp'
        Info: 2: + IC(1.935 ns) + CELL(0.666 ns) = 3.535 ns; Loc. = LCFF_X1_Y6_N1; Fanout = 1; REG Node = 'qn_temp~_emulated'
        Info: Total cell delay = 1.600 ns ( 45.26 % )
        Info: Total interconnect delay = 1.935 ns ( 54.74 % )
    Info: + Micro hold delay of destination is 0.306 ns
    Info: - Shortest pin to register delay is 2.603 ns
        Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; PIN Node = 'd'
        Info: 2: + IC(1.035 ns) + CELL(0.370 ns) = 2.495 ns; Loc. = LCCOMB_X1_Y6_N0; Fanout = 1; COMB Node = 'qn_temp~210'
        Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 2.603 ns; Loc. = LCFF_X1_Y6_N1; Fanout = 1; REG Node = 'qn_temp~_emulated'
        Info: Total cell delay = 1.568 ns ( 60.24 % )
        Info: Total interconnect delay = 1.035 ns ( 39.76 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 3 warnings
    Info: Allocated 103 megabytes of memory during processing
    Info: Processing ended: Sun May 27 20:57:17 2007
    Info: Elapsed time: 00:00:02