d.qsf

大量VHDL写的数字系统设计有用实例达到

# Copyright (C) 1991-2006 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		D_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


set_global_assignment -name FAMILY "Cyclone II"
set_global_assignment -name DEVICE EP2C8T144C8
set_global_assignment -name TOP_LEVEL_ENTITY D
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "6.0 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:44:38  MARCH 08, 2007"
set_global_assignment -name LAST_QUARTUS_VERSION 7.0
set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
set_global_assignment -name VHDL_FILE D.vhd
set_global_assignment -name VECTOR_WAVEFORM_FILE D.vwf
set_global_assignment -name SIMULATION_MODE TIMING
set_location_assignment IOBANK_2 -to cp
set_global_assignment -name VHDL_FILE "D:/my_eda/D/auk_dspip_lib_pkg.vhd"
set_global_assignment -name VHDL_FILE "D:/my_eda/D/auk_dspip_math_pkg.vhd"
set_global_assignment -name VHDL_FILE "D:/my_eda/D/auk_dspip_avalon_streaming_sink.vhd"
set_global_assignment -name VHDL_FILE "D:/my_eda/D/auk_dspip_avalon_streaming_source.vhd"
set_global_assignment -name VHDL_FILE "D:/my_eda/D/auk_dspip_avalon_streaming_controller.vhd"
set_global_assignment -name VERILOG_FILE "D:/my_eda/D/fir_st.v"
set_global_assignment -name VHDL_FILE "D:/my_eda/D/fir_new.vhd"
set_global_assignment -name VHDL_FILE "D:/my_eda/D/fir.vhd"
set_global_assignment -name USER_LIBRARIES "E:/altera/70/ip/fir_compiler/lib;"
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION ON -entity msft_data
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity tdl_da_lc
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity sadd_lpm
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity tsadd_lpm
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity sadd_lpm_cen
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity tsadd_lpm_cen
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity sadd
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity tsadd
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity lc_tdl_strat
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity lc_tdl_mr
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity lc_tdl_en
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity lc_tdl_strat_cen
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity sadd_reg_top_cen
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity tsadd_reg_top_cen
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity sadd_cen
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity sadd_reg_top
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity tsadd_reg_top
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity tsadd_lpm_reg_top_cen
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity sadd_lpm_reg_top_cen
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity mlu_nd_lc
set_global_assignment -name DSP_BLOCK_BALANCING "LOGIC ELEMENTS" -entity fir_st
set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE D.vwf