jian_cnt10.vhd

大量VHDL写的数字系统设计有用实例达到

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity jian_cnt10 is
port(clk,rst:in std_logic;
     q:out std_logic_vector(3 downto 0));
end;
architecture one of jian_cnt10 is
	signal q_temp:std_logic_vector(3 downto 0);
begin
process(clk,rst)
begin
if rst='1' then q_temp<="0000";
elsif clk'event and clk='1' then
if q_temp="0000" then q_temp<="1001";
else q_temp<=q_temp-1;
end if;
end if;
end process;
q<=q_temp;
end;