anyodd_div1.tan.qmsg

大量VHDL写的数字系统设计有用实例达到

{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk 1 " "Warning: Circuit may not operate. Detected 1 non-operational path(s) clocked by clock \"clk\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "clkdiv~reg0 clkdiv~reg0 clk 4.233 ns " "Info: Found hold time violation between source  pin or register \"clkdiv~reg0\" and destination pin or register \"clkdiv~reg0\" for clock \"clk\" (Hold time is 4.233 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "4.732 ns + Largest " "Info: + Largest clock skew is 4.732 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 9.623 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 9.623 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns clk~clkctrl 2 COMB CLKCTRL_G2 64 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 64; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.907 ns) + CELL(0.970 ns) 3.106 ns cnt1\[26\] 3 REG LCFF_X14_Y8_N21 3 " "Info: 3: + IC(0.907 ns) + CELL(0.970 ns) = 3.106 ns; Loc. = LCFF_X14_Y8_N21; Fanout = 3; REG Node = 'cnt1\[26\]'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "1.877 ns" { clk~clkctrl cnt1[26] } "NODE_NAME" } } { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.527 ns) + CELL(0.529 ns) 5.162 ns Equal0~339 4 COMB LCCOMB_X13_Y9_N20 1 " "Info: 4: + IC(1.527 ns) + CELL(0.529 ns) = 5.162 ns; Loc. = LCCOMB_X13_Y9_N20; Fanout = 1; COMB Node = 'Equal0~339'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "2.056 ns" { cnt1[26] Equal0~339 } "NODE_NAME" } } { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.396 ns) + CELL(0.650 ns) 6.208 ns Equal0~341 5 COMB LCCOMB_X13_Y9_N26 3 " "Info: 5: + IC(0.396 ns) + CELL(0.650 ns) = 6.208 ns; Loc. = LCCOMB_X13_Y9_N26; Fanout = 3; COMB Node = 'Equal0~341'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "1.046 ns" { Equal0~339 Equal0~341 } "NODE_NAME" } } { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.075 ns) + CELL(0.370 ns) 7.653 ns clk_temp~54 6 COMB LCCOMB_X10_Y9_N22 1 " "Info: 6: + IC(1.075 ns) + CELL(0.370 ns) = 7.653 ns; Loc. = LCCOMB_X10_Y9_N22; Fanout = 1; COMB Node = 'clk_temp~54'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "1.445 ns" { Equal0~341 clk_temp~54 } "NODE_NAME" } } { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.365 ns) + CELL(0.615 ns) 8.633 ns clk_temp~55 7 COMB LCCOMB_X10_Y9_N24 1 " "Info: 7: + IC(0.365 ns) + CELL(0.615 ns) = 8.633 ns; Loc. = LCCOMB_X10_Y9_N24; Fanout = 1; COMB Node = 'clk_temp~55'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.980 ns" { clk_temp~54 clk_temp~55 } "NODE_NAME" } } { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.324 ns) + CELL(0.666 ns) 9.623 ns clkdiv~reg0 8 REG LCFF_X10_Y9_N1 2 " "Info: 8: + IC(0.324 ns) + CELL(0.666 ns) = 9.623 ns; Loc. = LCFF_X10_Y9_N1; Fanout = 2; REG Node = 'clkdiv~reg0'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.990 ns" { clk_temp~55 clkdiv~reg0 } "NODE_NAME" } } { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.890 ns ( 50.82 % ) " "Info: Total cell delay = 4.890 ns ( 50.82 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.733 ns ( 49.18 % ) " "Info: Total interconnect delay = 4.733 ns ( 49.18 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "9.623 ns" { clk clk~clkctrl cnt1[26] Equal0~339 Equal0~341 clk_temp~54 clk_temp~55 clkdiv~reg0 } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "9.623 ns" { clk clk~combout clk~clkctrl cnt1[26] Equal0~339 Equal0~341 clk_temp~54 clk_temp~55 clkdiv~reg0 } { 0.000ns 0.000ns 0.139ns 0.907ns 1.527ns 0.396ns 1.075ns 0.365ns 0.324ns } { 0.000ns 1.090ns 0.000ns 0.970ns 0.529ns 0.650ns 0.370ns 0.615ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 4.891 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 4.891 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns clk~clkctrl 2 COMB CLKCTRL_G2 64 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 64; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.879 ns) + CELL(0.970 ns) 3.078 ns cnt2\[0\] 3 REG LCFF_X10_Y9_N15 4 " "Info: 3: + IC(0.879 ns) + CELL(0.970 ns) = 3.078 ns; Loc. = LCFF_X10_Y9_N15; Fanout = 4; REG Node = 'cnt2\[0\]'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "1.849 ns" { clk~clkctrl cnt2[0] } "NODE_NAME" } } { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.453 ns) + CELL(0.370 ns) 3.901 ns clk_temp~55 4 COMB LCCOMB_X10_Y9_N24 1 " "Info: 4: + IC(0.453 ns) + CELL(0.370 ns) = 3.901 ns; Loc. = LCCOMB_X10_Y9_N24; Fanout = 1; COMB Node = 'clk_temp~55'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.823 ns" { cnt2[0] clk_temp~55 } "NODE_NAME" } } { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.324 ns) + CELL(0.666 ns) 4.891 ns clkdiv~reg0 5 REG LCFF_X10_Y9_N1 2 " "Info: 5: + IC(0.324 ns) + CELL(0.666 ns) = 4.891 ns; Loc. = LCFF_X10_Y9_N1; Fanout = 2; REG Node = 'clkdiv~reg0'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.990 ns" { clk_temp~55 clkdiv~reg0 } "NODE_NAME" } } { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.096 ns ( 63.30 % ) " "Info: Total cell delay = 3.096 ns ( 63.30 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.795 ns ( 36.70 % ) " "Info: Total interconnect delay = 1.795 ns ( 36.70 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "4.891 ns" { clk clk~clkctrl cnt2[0] clk_temp~55 clkdiv~reg0 } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "4.891 ns" { clk clk~combout clk~clkctrl cnt2[0] clk_temp~55 clkdiv~reg0 } { 0.000ns 0.000ns 0.139ns 0.879ns 0.453ns 0.324ns } { 0.000ns 1.090ns 0.000ns 0.970ns 0.370ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "9.623 ns" { clk clk~clkctrl cnt1[26] Equal0~339 Equal0~341 clk_temp~54 clk_temp~55 clkdiv~reg0 } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "9.623 ns" { clk clk~combout clk~clkctrl cnt1[26] Equal0~339 Equal0~341 clk_temp~54 clk_temp~55 clkdiv~reg0 } { 0.000ns 0.000ns 0.139ns 0.907ns 1.527ns 0.396ns 1.075ns 0.365ns 0.324ns } { 0.000ns 1.090ns 0.000ns 0.970ns 0.529ns 0.650ns 0.370ns 0.615ns 0.666ns } } } { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "4.891 ns" { clk clk~clkctrl cnt2[0] clk_temp~55 clkdiv~reg0 } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "4.891 ns" { clk clk~combout clk~clkctrl cnt2[0] clk_temp~55 clkdiv~reg0 } { 0.000ns 0.000ns 0.139ns 0.879ns 0.453ns 0.324ns } { 0.000ns 1.090ns 0.000ns 0.970ns 0.370ns 0.666ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns - " "Info: - Micro clock to output delay of source is 0.304 ns" {  } { { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 54 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.501 ns - Shortest register register " "Info: - Shortest register to register delay is 0.501 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns clkdiv~reg0 1 REG LCFF_X10_Y9_N1 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X10_Y9_N1; Fanout = 2; REG Node = 'clkdiv~reg0'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "" { clkdiv~reg0 } "NODE_NAME" } } { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.393 ns) 0.393 ns clkdiv~8 2 COMB LCCOMB_X10_Y9_N0 1 " "Info: 2: + IC(0.000 ns) + CELL(0.393 ns) = 0.393 ns; Loc. = LCCOMB_X10_Y9_N0; Fanout = 1; COMB Node = 'clkdiv~8'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.393 ns" { clkdiv~reg0 clkdiv~8 } "NODE_NAME" } } { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 0.501 ns clkdiv~reg0 3 REG LCFF_X10_Y9_N1 2 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 0.501 ns; Loc. = LCFF_X10_Y9_N1; Fanout = 2; REG Node = 'clkdiv~reg0'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.108 ns" { clkdiv~8 clkdiv~reg0 } "NODE_NAME" } } { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.501 ns ( 100.00 % ) " "Info: Total cell delay = 0.501 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.501 ns" { clkdiv~reg0 clkdiv~8 clkdiv~reg0 } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "0.501 ns" { clkdiv~reg0 clkdiv~8 clkdiv~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 0.393ns 0.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" {  } { { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 54 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0}  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "9.623 ns" { clk clk~clkctrl cnt1[26] Equal0~339 Equal0~341 clk_temp~54 clk_temp~55 clkdiv~reg0 } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "9.623 ns" { clk clk~combout clk~clkctrl cnt1[26] Equal0~339 Equal0~341 clk_temp~54 clk_temp~55 clkdiv~reg0 } { 0.000ns 0.000ns 0.139ns 0.907ns 1.527ns 0.396ns 1.075ns 0.365ns 0.324ns } { 0.000ns 1.090ns 0.000ns 0.970ns 0.529ns 0.650ns 0.370ns 0.615ns 0.666ns } } } { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosur