📄 anyodd_div1.tan.qmsg

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💻 QMSG
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{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "82 " "Warning: Found 82 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "cnt2\[27\] " "Info: Detected ripple clock \"cnt2\[27\]\" as buffer" {  } { { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 27 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt2\[27\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt2\[28\] " "Info: Detected ripple clock \"cnt2\[28\]\" as buffer" {  } { { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 27 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt2\[28\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt2\[18\] " "Info: Detected ripple clock \"cnt2\[18\]\" as buffer" {  } { { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 27 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt2\[18\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt2\[16\] " "Info: Detected ripple clock \"cnt2\[16\]\" as buffer" {  } { { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 27 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt2\[16\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt2\[17\] " "Info: Detected ripple clock \"cnt2\[17\]\" as buffer" {  } { { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 27 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt2\[17\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt2\[15\] " "Info: Detected ripple clock \"cnt2\[15\]\" as buffer" {  } { { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 27 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt2\[15\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt2\[8\] " "Info: Detected ripple clock \"cnt2\[8\]\" as buffer" {  } { { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 27 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt2\[8\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt2\[10\] " "Info: Detected ripple clock \"cnt2\[10\]\" as buffer" {  } { { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 27 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt2\[10\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt2\[9\] " "Info: Detected ripple clock \"cnt2\[9\]\" as buffer" {  } { { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 27 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt2\[9\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt2\[7\] " "Info: Detected ripple clock \"cnt2\[7\]\" as buffer" {  } { { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 27 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt2\[7\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt2\[4\] " "Info: Detected ripple clock \"cnt2\[4\]\" as buffer" {  } { { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 27 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt2\[4\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt2\[5\] " "Info: Detected ripple clock \"cnt2\[5\]\" as buffer" {  } { { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 27 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt2\[5\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt2\[3\] " "Info: Detected ripple clock \"cnt2\[3\]\" as buffer" {  } { { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 27 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt2\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt2\[6\] " "Info: Detected ripple clock \"cnt2\[6\]\" as buffer" {  } { { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 27 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt2\[6\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt2\[12\] " "Info: Detected ripple clock \"cnt2\[12\]\" as buffer" {  } { { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 27 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt2\[12\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt2\[14\] " "Info: Detected ripple clock \"cnt2\[14\]\" as buffer" {  } { { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 27 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt2\[14\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt2\[13\] " "Info: Detected ripple clock \"cnt2\[13\]\" as buffer" {  } { { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 27 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt2\[13\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt2\[11\] " "Info: Detected ripple clock \"cnt2\[11\]\" as buffer" {  } { { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 27 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt2\[11\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt2\[25\] " "Info: Detected ripple clock \"cnt2\[25\]\" as buffer" {  } { { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 27 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt2\[25\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt2\[26\] " "Info: Detected ripple clock \"cnt2\[26\]\" as buffer" {  } { { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 27 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt2\[26\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt2\[24\] " "Info: Detected ripple clock \"cnt2\[24\]\" as buffer" {  } { { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 27 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt2\[24\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt2\[23\] " "Info: Detected ripple clock \"cnt2\[23\]\" as buffer" {  } { { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 27 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt2\[23\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt2\[22\] " "Info: Detected ripple clock \"cnt2\[22\]\" as buffer" {  } { { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 27 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt2\[22\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt2\[21\] " "Info: Detected ripple clock \"cnt2\[21\]\" as buffer" {  } { { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 27 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt2\[21\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt2\[20\] " "Info: Detected ripple clock \"cnt2\[20\]\" as buffer" {  } { { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 27 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt2\[20\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt2\[19\] " "Info: Detected ripple clock \"cnt2\[19\]\" as buffer" {  } { { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 27 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt2\[19\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt2\[29\] " "Info: Detected ripple clock \"cnt2\[29\]\" as buffer" {  } { { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 27 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt2\[29\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt2\[30\] " "Info: Detected ripple clock \"cnt2\[30\]\" as buffer" {  } { { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 27 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt2\[30\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt2\[31\] " "Info: Detected ripple clock \"cnt2\[31\]\" as buffer" {  } { { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 27 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt2\[31\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "Equal1~333 " "Info: Detected gated clock \"Equal1~333\" as buffer" {  } { { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 28 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "Equal1~333" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "Equal1~329 " "Info: Detected gated clock \"Equal1~329\" as buffer" {  } { { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 28 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "Equal1~329" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "Equal1~327 " "Info: Detected gated clock \"Equal1~327\" as buffer" {  } { { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 28 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "Equal1~327" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "Equal1~326 " "Info: Detected gated clock \"Equal1~326\" as buffer" {  } { { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 28 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "Equal1~326" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "Equal1~328 " "Info: Detected gated clock \"Equal1~328\" as buffer" {  } { { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 28 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "Equal1~328" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt1\[21\] " "Info: Detected ripple clock \"cnt1\[21\]\" as buffer" {  } { { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 17 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt1\[21\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt1\[20\] " "Info: Detected ripple clock \"cnt1\[20\]\" as buffer" {  } { { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 17 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt1\[20\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt1\[22\] " "Info: Detected ripple clock \"cnt1\[22\]\" as buffer" {  } { { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 17 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt1\[22\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt1\[19\] " "Info: Detected ripple clock \"cnt1\[19\]\" as buffer" {  } { { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 17 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt1\[19\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt1\[28\] " "Info: Detected ripple clock \"cnt1\[28\]\" as buffer" {  } { { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 17 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt1\[28\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt1\[29\] " "Info: Detected ripple clock \"cnt1\[29\]\" as buffer" {  } { { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 17 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt1\[29\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt1\[30\] " "Info: Detected ripple clock \"cnt1\[30\]\" as buffer" {  } { { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 17 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt1\[30\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt1\[27\] " "Info: Detected ripple clock \"cnt1\[27\]\" as buffer" {  } { { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 17 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt1\[27\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt1\[23\] " "Info: Detected ripple clock \"cnt1\[23\]\" as buffer" {  } { { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 17 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt1\[23\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt1\[25\] " "Info: Detected ripple clock \"cnt1\[25\]\" as buffer" {  } { { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 17 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt1\[25\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt1\[26\] " "Info: Detected ripple clock \"cnt1\[26\]\" as buffer" {  } { { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 17 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt1\[26\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt1\[24\] " "Info: Detected ripple clock \"cnt1\[24\]\" as buffer" {  } { { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 17 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt1\[24\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt1\[5\] " "Info: Detected ripple clock \"cnt1\[5\]\" as buffer" {  } { { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 17 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt1\[5\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt1\[6\] " "Info: Detected ripple clock \"cnt1\[6\]\" as buffer" {  } { { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 17 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt1\[6\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt1\[3\] " "Info: Detected ripple clock \"cnt1\[3\]\" as buffer" {  } { { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 17 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt1\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt1\[4\] " "Info: Detected ripple clock \"cnt1\[4\]\" as buffer" {  } { { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 17 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt1\[4\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt1\[17\] " "Info: Detected ripple clock \"cnt1\[17\]\" as buffer" {  } { { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 17 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt1\[17\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt1\[18\] " "Info: Detected ripple clock \"cnt1\[18\]\" as buffer" {  } { { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 17 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt1\[18\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt1\[16\] " "Info: Detected ripple clock \"cnt1\[16\]\" as buffer" {  } { { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 17 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt1\[16\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt1\[15\] " "Info: Detected ripple clock \"cnt1\[15\]\" as buffer" {  } { { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 17 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt1\[15\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt1\[11\] " "Info: Detected ripple clock \"cnt1\[11\]\" as buffer" {  } { { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 17 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt1\[11\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt1\[13\] " "Info: Detected ripple clock \"cnt1\[13\]\" as buffer" {  } { { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 17 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt1\[13\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt1\[14\] " "Info: Detected ripple clock \"cnt1\[14\]\" as buffer" {  } { { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 17 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt1\[14\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt1\[12\] " "Info: Detected ripple clock \"cnt1\[12\]\" as buffer" {  } { { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 17 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt1\[12\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt1\[9\] " "Info: Detected ripple clock \"cnt1\[9\]\" as buffer" {  } { { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 17 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt1\[9\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt1\[7\] " "Info: Detected ripple clock \"cnt1\[7\]\" as buffer" {  } { { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 17 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt1\[7\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt1\[10\] " "Info: Detected ripple clock \"cnt1\[10\]\" as buffer" {  } { { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 17 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt1\[10\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt1\[8\] " "Info: Detected ripple clock \"cnt1\[8\]\" as buffer" {  } { { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 17 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt1\[8\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "Equal1~332 " "Info: Detected gated clock \"Equal1~332\" as buffer" {  } { { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 28 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "Equal1~332" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "Equal1~331 " "Info: Detected gated clock \"Equal1~331\" as buffer" {  } { { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 28 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "Equal1~331" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "Equal1~334 " "Info: Detected gated clock \"Equal1~334\" as buffer" {  } { { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 28 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "Equal1~334" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt1\[31\] " "Info: Detected ripple clock \"cnt1\[31\]\" as buffer" {  } { { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 17 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt1\[31\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "Equal0~338 " "Info: Detected gated clock \"Equal0~338\" as buffer" {  } { { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 18 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "Equal0~338" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "Equal0~340 " "Info: Detected gated clock \"Equal0~340\" as buffer" {  } { { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 18 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "Equal0~340" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "Equal0~339 " "Info: Detected gated clock \"Equal0~339\" as buffer" {  } { { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 18 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "Equal0~339" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt2\[2\] " "Info: Detected ripple clock \"cnt2\[2\]\" as buffer" {  } { { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 27 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt2\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt1\[0\] " "Info: Detected ripple clock \"cnt1\[0\]\" as buffer" {  } { { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 17 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt1\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt1\[2\] " "Info: Detected ripple clock \"cnt1\[2\]\" as buffer" {  } { { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 17 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt1\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "Equal0~333 " "Info: Detected gated clock \"Equal0~333\" as buffer" {  } { { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 18 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "Equal0~333" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "Equal0~336 " "Info: Detected gated clock \"Equal0~336\" as buffer" {  } { { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 18 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "Equal0~336" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "Equal0~335 " "Info: Detected gated clock \"Equal0~335\" as buffer" {  } { { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 18 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "Equal0~335" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "Equal0~334 " "Info: Detected gated clock \"Equal0~334\" as buffer" {  } { { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 18 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "Equal0~334" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "Equal0~341 " "Info: Detected gated clock \"Equal0~341\" as buffer" {  } { { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 18 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "Equal0~341" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "clk_temp~53 " "Info: Detected gated clock \"clk_temp~53\" as buffer" {  } { { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 12 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "clk_temp~53" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt2\[1\] " "Info: Detected ripple clock \"cnt2\[1\]\" as buffer" {  } { { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 27 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt2\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt2\[0\] " "Info: Detected ripple clock \"cnt2\[0\]\" as buffer" {  } { { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 27 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt2\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt1\[1\] " "Info: Detected ripple clock \"cnt1\[1\]\" as buffer" {  } { { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 17 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt1\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "clk_temp~55 " "Info: Detected gated clock \"clk_temp~55\" as buffer" {  } { { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 12 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "clk_temp~55" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register clkdiv~reg0 register clkdiv~reg0 181.92 MHz 5.497 ns Internal " "Info: Clock \"clk\" has Internal fmax of 181.92 MHz between source register \"clkdiv~reg0\" and destination register \"clkdiv~reg0\" (period= 5.497 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.501 ns + Longest register register " "Info: + Longest register to register delay is 0.501 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns clkdiv~reg0 1 REG LCFF_X10_Y9_N1 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X10_Y9_N1; Fanout = 2; REG Node = 'clkdiv~reg0'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "" { clkdiv~reg0 } "NODE_NAME" } } { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.393 ns) 0.393 ns clkdiv~8 2 COMB LCCOMB_X10_Y9_N0 1 " "Info: 2: + IC(0.000 ns) + CELL(0.393 ns) = 0.393 ns; Loc. = LCCOMB_X10_Y9_N0; Fanout = 1; COMB Node = 'clkdiv~8'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.393 ns" { clkdiv~reg0 clkdiv~8 } "NODE_NAME" } } { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 0.501 ns clkdiv~reg0 3 REG LCFF_X10_Y9_N1 2 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 0.501 ns; Loc. = LCFF_X10_Y9_N1; Fanout = 2; REG Node = 'clkdiv~reg0'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.108 ns" { clkdiv~8 clkdiv~reg0 } "NODE_NAME" } } { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.501 ns ( 100.00 % ) " "Info: Total cell delay = 0.501 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.501 ns" { clkdiv~reg0 clkdiv~8 clkdiv~reg0 } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "0.501 ns" { clkdiv~reg0 clkdiv~8 clkdiv~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 0.393ns 0.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-4.732 ns - Smallest " "Info: - Smallest clock skew is -4.732 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 4.891 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 4.891 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns clk~clkctrl 2 COMB CLKCTRL_G2 64 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 64; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.879 ns) + CELL(0.970 ns) 3.078 ns cnt2\[0\] 3 REG LCFF_X10_Y9_N15 4 " "Info: 3: + IC(0.879 ns) + CELL(0.970 ns) = 3.078 ns; Loc. = LCFF_X10_Y9_N15; Fanout = 4; REG Node = 'cnt2\[0\]'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "1.849 ns" { clk~clkctrl cnt2[0] } "NODE_NAME" } } { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.453 ns) + CELL(0.370 ns) 3.901 ns clk_temp~55 4 COMB LCCOMB_X10_Y9_N24 1 " "Info: 4: + IC(0.453 ns) + CELL(0.370 ns) = 3.901 ns; Loc. = LCCOMB_X10_Y9_N24; Fanout = 1; COMB Node = 'clk_temp~55'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.823 ns" { cnt2[0] clk_temp~55 } "NODE_NAME" } } { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.324 ns) + CELL(0.666 ns) 4.891 ns clkdiv~reg0 5 REG LCFF_X10_Y9_N1 2 " "Info: 5: + IC(0.324 ns) + CELL(0.666 ns) = 4.891 ns; Loc. = LCFF_X10_Y9_N1; Fanout = 2; REG Node = 'clkdiv~reg0'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.990 ns" { clk_temp~55 clkdiv~reg0 } "NODE_NAME" } } { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.096 ns ( 63.30 % ) " "Info: Total cell delay = 3.096 ns ( 63.30 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.795 ns ( 36.70 % ) " "Info: Total interconnect delay = 1.795 ns ( 36.70 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "4.891 ns" { clk clk~clkctrl cnt2[0] clk_temp~55 clkdiv~reg0 } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "4.891 ns" { clk clk~combout clk~clkctrl cnt2[0] clk_temp~55 clkdiv~reg0 } { 0.000ns 0.000ns 0.139ns 0.879ns 0.453ns 0.324ns } { 0.000ns 1.090ns 0.000ns 0.970ns 0.370ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 9.623 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 9.623 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns clk~clkctrl 2 COMB CLKCTRL_G2 64 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 64; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.907 ns) + CELL(0.970 ns) 3.106 ns cnt1\[26\] 3 REG LCFF_X14_Y8_N21 3 " "Info: 3: + IC(0.907 ns) + CELL(0.970 ns) = 3.106 ns; Loc. = LCFF_X14_Y8_N21; Fanout = 3; REG Node = 'cnt1\[26\]'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "1.877 ns" { clk~clkctrl cnt1[26] } "NODE_NAME" } } { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.527 ns) + CELL(0.529 ns) 5.162 ns Equal0~339 4 COMB LCCOMB_X13_Y9_N20 1 " "Info: 4: + IC(1.527 ns) + CELL(0.529 ns) = 5.162 ns; Loc. = LCCOMB_X13_Y9_N20; Fanout = 1; COMB Node = 'Equal0~339'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "2.056 ns" { cnt1[26] Equal0~339 } "NODE_NAME" } } { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.396 ns) + CELL(0.650 ns) 6.208 ns Equal0~341 5 COMB LCCOMB_X13_Y9_N26 3 " "Info: 5: + IC(0.396 ns) + CELL(0.650 ns) = 6.208 ns; Loc. = LCCOMB_X13_Y9_N26; Fanout = 3; COMB Node = 'Equal0~341'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "1.046 ns" { Equal0~339 Equal0~341 } "NODE_NAME" } } { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.075 ns) + CELL(0.370 ns) 7.653 ns clk_temp~54 6 COMB LCCOMB_X10_Y9_N22 1 " "Info: 6: + IC(1.075 ns) + CELL(0.370 ns) = 7.653 ns; Loc. = LCCOMB_X10_Y9_N22; Fanout = 1; COMB Node = 'clk_temp~54'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "1.445 ns" { Equal0~341 clk_temp~54 } "NODE_NAME" } } { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.365 ns) + CELL(0.615 ns) 8.633 ns clk_temp~55 7 COMB LCCOMB_X10_Y9_N24 1 " "Info: 7: + IC(0.365 ns) + CELL(0.615 ns) = 8.633 ns; Loc. = LCCOMB_X10_Y9_N24; Fanout = 1; COMB Node = 'clk_temp~55'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.980 ns" { clk_temp~54 clk_temp~55 } "NODE_NAME" } } { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.324 ns) + CELL(0.666 ns) 9.623 ns clkdiv~reg0 8 REG LCFF_X10_Y9_N1 2 " "Info: 8: + IC(0.324 ns) + CELL(0.666 ns) = 9.623 ns; Loc. = LCFF_X10_Y9_N1; Fanout = 2; REG Node = 'clkdiv~reg0'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.990 ns" { clk_temp~55 clkdiv~reg0 } "NODE_NAME" } } { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.890 ns ( 50.82 % ) " "Info: Total cell delay = 4.890 ns ( 50.82 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.733 ns ( 49.18 % ) " "Info: Total interconnect delay = 4.733 ns ( 49.18 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "9.623 ns" { clk clk~clkctrl cnt1[26] Equal0~339 Equal0~341 clk_temp~54 clk_temp~55 clkdiv~reg0 } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "9.623 ns" { clk clk~combout clk~clkctrl cnt1[26] Equal0~339 Equal0~341 clk_temp~54 clk_temp~55 clkdiv~reg0 } { 0.000ns 0.000ns 0.139ns 0.907ns 1.527ns 0.396ns 1.075ns 0.365ns 0.324ns } { 0.000ns 1.090ns 0.000ns 0.970ns 0.529ns 0.650ns 0.370ns 0.615ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "4.891 ns" { clk clk~clkctrl cnt2[0] clk_temp~55 clkdiv~reg0 } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "4.891 ns" { clk clk~combout clk~clkctrl cnt2[0] clk_temp~55 clkdiv~reg0 } { 0.000ns 0.000ns 0.139ns 0.879ns 0.453ns 0.324ns } { 0.000ns 1.090ns 0.000ns 0.970ns 0.370ns 0.666ns } } } { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "9.623 ns" { clk clk~clkctrl cnt1[26] Equal0~339 Equal0~341 clk_temp~54 clk_temp~55 clkdiv~reg0 } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "9.623 ns" { clk clk~combout clk~clkctrl cnt1[26] Equal0~339 Equal0~341 clk_temp~54 clk_temp~55 clkdiv~reg0 } { 0.000ns 0.000ns 0.139ns 0.907ns 1.527ns 0.396ns 1.075ns 0.365ns 0.324ns } { 0.000ns 1.090ns 0.000ns 0.970ns 0.529ns 0.650ns 0.370ns 0.615ns 0.666ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 54 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "anyodd_div1.vhd" "" { Text "D:/my_eda/anyodd_div1/anyodd_div1.vhd" 54 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.501 ns" { clkdiv~reg0 clkdiv~8 clkdiv~reg0 } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "0.501 ns" { clkdiv~reg0 clkdiv~8 clkdiv~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 0.393ns 0.108ns } } } { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "4.891 ns" { clk clk~clkctrl cnt2[0] clk_temp~55 clkdiv~reg0 } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "4.891 ns" { clk clk~combout clk~clkctrl cnt2[0] clk_temp~55 clkdiv~reg0 } { 0.000ns 0.000ns 0.139ns 0.879ns 0.453ns 0.324ns } { 0.000ns 1.090ns 0.000ns 0.970ns 0.370ns 0.666ns } } } { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "9.623 ns" { clk clk~clkctrl cnt1[26] Equal0~339 Equal0~341 clk_temp~54 clk_temp~55 clkdiv~reg0 } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "9.623 ns" { clk clk~combout clk~clkctrl cnt1[26] Equal0~339 Equal0~341 clk_temp~54 clk_temp~55 clkdiv~reg0 } { 0.000ns 0.000ns 0.139ns 0.907ns 1.527ns 0.396ns 1.075ns 0.365ns 0.324ns } { 0.000ns 1.090ns 0.000ns 0.970ns 0.529ns 0.650ns 0.370ns 0.615ns 0.666ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
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