anyodd_div1.tan.rpt

大量VHDL写的数字系统设计有用实例达到

    Info: Detected ripple clock "cnt2[19]" as buffer
    Info: Detected ripple clock "cnt2[29]" as buffer
    Info: Detected ripple clock "cnt2[30]" as buffer
    Info: Detected ripple clock "cnt2[31]" as buffer
    Info: Detected gated clock "Equal1~333" as buffer
    Info: Detected gated clock "Equal1~329" as buffer
    Info: Detected gated clock "Equal1~327" as buffer
    Info: Detected gated clock "Equal1~326" as buffer
    Info: Detected gated clock "Equal1~328" as buffer
    Info: Detected ripple clock "cnt1[21]" as buffer
    Info: Detected ripple clock "cnt1[20]" as buffer
    Info: Detected ripple clock "cnt1[22]" as buffer
    Info: Detected ripple clock "cnt1[19]" as buffer
    Info: Detected ripple clock "cnt1[28]" as buffer
    Info: Detected ripple clock "cnt1[29]" as buffer
    Info: Detected ripple clock "cnt1[30]" as buffer
    Info: Detected ripple clock "cnt1[27]" as buffer
    Info: Detected ripple clock "cnt1[23]" as buffer
    Info: Detected ripple clock "cnt1[25]" as buffer
    Info: Detected ripple clock "cnt1[26]" as buffer
    Info: Detected ripple clock "cnt1[24]" as buffer
    Info: Detected ripple clock "cnt1[5]" as buffer
    Info: Detected ripple clock "cnt1[6]" as buffer
    Info: Detected ripple clock "cnt1[3]" as buffer
    Info: Detected ripple clock "cnt1[4]" as buffer
    Info: Detected ripple clock "cnt1[17]" as buffer
    Info: Detected ripple clock "cnt1[18]" as buffer
    Info: Detected ripple clock "cnt1[16]" as buffer
    Info: Detected ripple clock "cnt1[15]" as buffer
    Info: Detected ripple clock "cnt1[11]" as buffer
    Info: Detected ripple clock "cnt1[13]" as buffer
    Info: Detected ripple clock "cnt1[14]" as buffer
    Info: Detected ripple clock "cnt1[12]" as buffer
    Info: Detected ripple clock "cnt1[9]" as buffer
    Info: Detected ripple clock "cnt1[7]" as buffer
    Info: Detected ripple clock "cnt1[10]" as buffer
    Info: Detected ripple clock "cnt1[8]" as buffer
    Info: Detected gated clock "Equal1~332" as buffer
    Info: Detected gated clock "Equal1~331" as buffer
    Info: Detected gated clock "Equal1~334" as buffer
    Info: Detected ripple clock "cnt1[31]" as buffer
    Info: Detected gated clock "Equal0~338" as buffer
    Info: Detected gated clock "Equal0~340" as buffer
    Info: Detected gated clock "Equal0~339" as buffer
    Info: Detected ripple clock "cnt2[2]" as buffer
    Info: Detected ripple clock "cnt1[0]" as buffer
    Info: Detected ripple clock "cnt1[2]" as buffer
    Info: Detected gated clock "Equal0~333" as buffer
    Info: Detected gated clock "Equal0~336" as buffer
    Info: Detected gated clock "Equal0~335" as buffer
    Info: Detected gated clock "Equal0~334" as buffer
    Info: Detected gated clock "Equal0~341" as buffer
    Info: Detected gated clock "clk_temp~53" as buffer
    Info: Detected ripple clock "cnt2[1]" as buffer
    Info: Detected ripple clock "cnt2[0]" as buffer
    Info: Detected ripple clock "cnt1[1]" as buffer
    Info: Detected gated clock "clk_temp~55" as buffer
Info: Clock "clk" has Internal fmax of 181.92 MHz between source register "clkdiv~reg0" and destination register "clkdiv~reg0" (period= 5.497 ns)
    Info: + Longest register to register delay is 0.501 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X10_Y9_N1; Fanout = 2; REG Node = 'clkdiv~reg0'
        Info: 2: + IC(0.000 ns) + CELL(0.393 ns) = 0.393 ns; Loc. = LCCOMB_X10_Y9_N0; Fanout = 1; COMB Node = 'clkdiv~8'
        Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 0.501 ns; Loc. = LCFF_X10_Y9_N1; Fanout = 2; REG Node = 'clkdiv~reg0'
        Info: Total cell delay = 0.501 ns ( 100.00 % )
    Info: - Smallest clock skew is -4.732 ns
        Info: + Shortest clock path from clock "clk" to destination register is 4.891 ns
            Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
            Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 64; COMB Node = 'clk~clkctrl'
            Info: 3: + IC(0.879 ns) + CELL(0.970 ns) = 3.078 ns; Loc. = LCFF_X10_Y9_N15; Fanout = 4; REG Node = 'cnt2[0]'
            Info: 4: + IC(0.453 ns) + CELL(0.370 ns) = 3.901 ns; Loc. = LCCOMB_X10_Y9_N24; Fanout = 1; COMB Node = 'clk_temp~55'
            Info: 5: + IC(0.324 ns) + CELL(0.666 ns) = 4.891 ns; Loc. = LCFF_X10_Y9_N1; Fanout = 2; REG Node = 'clkdiv~reg0'
            Info: Total cell delay = 3.096 ns ( 63.30 % )
            Info: Total interconnect delay = 1.795 ns ( 36.70 % )
        Info: - Longest clock path from clock "clk" to source register is 9.623 ns
            Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
            Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 64; COMB Node = 'clk~clkctrl'
            Info: 3: + IC(0.907 ns) + CELL(0.970 ns) = 3.106 ns; Loc. = LCFF_X14_Y8_N21; Fanout = 3; REG Node = 'cnt1[26]'
            Info: 4: + IC(1.527 ns) + CELL(0.529 ns) = 5.162 ns; Loc. = LCCOMB_X13_Y9_N20; Fanout = 1; COMB Node = 'Equal0~339'
            Info: 5: + IC(0.396 ns) + CELL(0.650 ns) = 6.208 ns; Loc. = LCCOMB_X13_Y9_N26; Fanout = 3; COMB Node = 'Equal0~341'
            Info: 6: + IC(1.075 ns) + CELL(0.370 ns) = 7.653 ns; Loc. = LCCOMB_X10_Y9_N22; Fanout = 1; COMB Node = 'clk_temp~54'
            Info: 7: + IC(0.365 ns) + CELL(0.615 ns) = 8.633 ns; Loc. = LCCOMB_X10_Y9_N24; Fanout = 1; COMB Node = 'clk_temp~55'
            Info: 8: + IC(0.324 ns) + CELL(0.666 ns) = 9.623 ns; Loc. = LCFF_X10_Y9_N1; Fanout = 2; REG Node = 'clkdiv~reg0'
            Info: Total cell delay = 4.890 ns ( 50.82 % )
            Info: Total interconnect delay = 4.733 ns ( 49.18 % )
    Info: + Micro clock to output delay of source is 0.304 ns
    Info: + Micro setup delay of destination is -0.040 ns
Warning: Circuit may not operate. D