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📄 anyodd_div1.tan.rpt

📁 大量VHDL写的数字系统设计有用实例达到
💻 RPT
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; N/A                                     ; 255.04 MHz ( period = 3.921 ns )                    ; cnt1[7]     ; cnt1[28]    ; clk        ; clk      ; None                        ; None                      ; 3.676 ns                ;
; N/A                                     ; 255.36 MHz ( period = 3.916 ns )                    ; cnt2[4]     ; cnt2[25]    ; clk        ; clk      ; None                        ; None                      ; 3.670 ns                ;
; N/A                                     ; 255.43 MHz ( period = 3.915 ns )                    ; cnt1[4]     ; cnt1[25]    ; clk        ; clk      ; None                        ; None                      ; 3.670 ns                ;
; N/A                                     ; 256.28 MHz ( period = 3.902 ns )                    ; cnt2[9]     ; cnt2[31]    ; clk        ; clk      ; None                        ; None                      ; 3.656 ns                ;
; N/A                                     ; 256.34 MHz ( period = 3.901 ns )                    ; cnt1[9]     ; cnt1[31]    ; clk        ; clk      ; None                        ; None                      ; 3.656 ns                ;
; N/A                                     ; 256.34 MHz ( period = 3.901 ns )                    ; cnt2[1]     ; cnt2[23]    ; clk        ; clk      ; None                        ; None                      ; 3.655 ns                ;
; N/A                                     ; 256.41 MHz ( period = 3.900 ns )                    ; cnt1[1]     ; cnt1[23]    ; clk        ; clk      ; None                        ; None                      ; 3.655 ns                ;
; N/A                                     ; 256.54 MHz ( period = 3.898 ns )                    ; cnt1[0]     ; cnt1[19]    ; clk        ; clk      ; None                        ; None                      ; 3.653 ns                ;
; N/A                                     ; 256.81 MHz ( period = 3.894 ns )                    ; cnt1[22]    ; cnt1[0]     ; clk        ; clk      ; None                        ; None                      ; 3.611 ns                ;
; N/A                                     ; 256.87 MHz ( period = 3.893 ns )                    ; cnt2[4]     ; cnt2[0]     ; clk        ; clk      ; None                        ; None                      ; 3.630 ns                ;
; N/A                                     ; 256.94 MHz ( period = 3.892 ns )                    ; cnt2[4]     ; cnt2[2]     ; clk        ; clk      ; None                        ; None                      ; 3.629 ns                ;
; N/A                                     ; 257.40 MHz ( period = 3.885 ns )                    ; cnt2[6]     ; cnt2[26]    ; clk        ; clk      ; None                        ; None                      ; 3.639 ns                ;
; N/A                                     ; 257.40 MHz ( period = 3.885 ns )                    ; cnt2[5]     ; cnt2[25]    ; clk        ; clk      ; None                        ; None                      ; 3.639 ns                ;
; N/A                                     ; 257.47 MHz ( period = 3.884 ns )                    ; cnt1[6]     ; cnt1[26]    ; clk        ; clk      ; None                        ; None                      ; 3.639 ns                ;
; N/A                                     ; 257.47 MHz ( period = 3.884 ns )                    ; cnt1[5]     ; cnt1[25]    ; clk        ; clk      ; None                        ; None                      ; 3.639 ns                ;
; N/A                                     ; 258.60 MHz ( period = 3.867 ns )                    ; cnt1[21]    ; cnt1[2]     ; clk        ; clk      ; None                        ; None                      ; 3.584 ns                ;
; N/A                                     ; 258.67 MHz ( period = 3.866 ns )                    ; cnt2[10]    ; cnt2[31]    ; clk        ; clk      ; None                        ; None                      ; 3.620 ns                ;
; N/A                                     ; 258.67 MHz ( period = 3.866 ns )                    ; cnt2[8]     ; cnt2[29]    ; clk        ; clk      ; None                        ; None                      ; 3.620 ns                ;
; N/A                                     ; 258.73 MHz ( period = 3.865 ns )                    ; cnt1[10]    ; cnt1[31]    ; clk        ; clk      ; None                        ; None                      ; 3.620 ns                ;
; N/A                                     ; 258.73 MHz ( period = 3.865 ns )                    ; cnt1[8]     ; cnt1[29]    ; clk        ; clk      ; None                        ; None                      ; 3.620 ns                ;
; N/A                                     ; 258.80 MHz ( period = 3.864 ns )                    ; cnt2[2]     ; cnt2[21]    ; clk        ; clk      ; None                        ; None                      ; 3.617 ns                ;
; N/A                                     ; 259.27 MHz ( period = 3.857 ns )                    ; cnt1[19]    ; cnt1[2]     ; clk        ; clk      ; None                        ; None                      ; 3.574 ns                ;
; N/A                                     ; 259.40 MHz ( period = 3.855 ns )                    ; cnt2[0]     ; cnt2[19]    ; clk        ; clk      ; None                        ; None                      ; 3.608 ns                ;
; N/A                                     ; 259.74 MHz ( period = 3.850 ns )                    ; cnt2[10]    ; cnt2[0]     ; clk        ; clk      ; None                        ; None                      ; 3.587 ns                ;
; N/A                                     ; 259.74 MHz ( period = 3.850 ns )                    ; cnt1[2]     ; cnt1[20]    ; clk        ; clk      ; None                        ; None                      ; 3.605 ns                ;
; N/A                                     ; 259.81 MHz ( period = 3.849 ns )                    ; cnt2[10]    ; cnt2[2]     ; clk        ; clk      ; None                        ; None                      ; 3.586 ns                ;
; N/A                                     ; 260.69 MHz ( period = 3.836 ns )                    ; cnt2[7]     ; cnt2[27]    ; clk        ; clk      ; None                        ; None                      ; 3.590 ns                ;
; N/A                                     ; 260.76 MHz ( period = 3.835 ns )                    ; cnt1[7]     ; cnt1[27]    ; clk        ; clk      ; None                        ; None                      ; 3.590 ns                ;
; N/A                                     ; 261.10 MHz ( period = 3.830 ns )                    ; cnt2[4]     ; cnt2[24]    ; clk        ; clk      ; None                        ; None                      ; 3.584 ns                ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;             ;             ;            ;          ;                             ;                           ;                         ;
+-----------------------------------------+-----------------------------------------------------+-------------+-------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Hold: 'clk'                                                                                                                                                                 ;
+------------------------------------------+-------------+-------------+------------+----------+----------------------------+----------------------------+--------------------------+
; Minimum Slack                            ; From        ; To          ; From Clock ; To Clock ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ;
+------------------------------------------+-------------+-------------+------------+----------+----------------------------+----------------------------+--------------------------+
; Not operational: Clock Skew > Data Delay ; clkdiv~reg0 ; clkdiv~reg0 ; clk        ; clk      ; None                       ; None                       ; 0.501 ns                 ;
+------------------------------------------+-------------+-------------+------------+----------+----------------------------+----------------------------+--------------------------+


+-----------------------------------------------------------------------+
; tco                                                                   ;
+-------+--------------+------------+-------------+--------+------------+
; Slack ; Required tco ; Actual tco ; From        ; To     ; From Clock ;
+-------+--------------+------------+-------------+--------+------------+
; N/A   ; None         ; 15.090 ns  ; clkdiv~reg0 ; clkdiv ; clk        ;
+-------+--------------+------------+-------------+--------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version
    Info: Processing started: Tue Mar 27 22:24:11 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off anyodd_div1 -c anyodd_div1 --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Warning: Found 82 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "cnt2[27]" as buffer
    Info: Detected ripple clock "cnt2[28]" as buffer
    Info: Detected ripple clock "cnt2[18]" as buffer
    Info: Detected ripple clock "cnt2[16]" as buffer
    Info: Detected ripple clock "cnt2[17]" as buffer
    Info: Detected ripple clock "cnt2[15]" as buffer
    Info: Detected ripple clock "cnt2[8]" as buffer
    Info: Detected ripple clock "cnt2[10]" as buffer
    Info: Detected ripple clock "cnt2[9]" as buffer
    Info: Detected ripple clock "cnt2[7]" as buffer
    Info: Detected ripple clock "cnt2[4]" as buffer
    Info: Detected ripple clock "cnt2[5]" as buffer
    Info: Detected ripple clock "cnt2[3]" as buffer
    Info: Detected ripple clock "cnt2[6]" as buffer
    Info: Detected ripple clock "cnt2[12]" as buffer
    Info: Detected ripple clock "cnt2[14]" as buffer
    Info: Detected ripple clock "cnt2[13]" as buffer
    Info: Detected ripple clock "cnt2[11]" as buffer
    Info: Detected ripple clock "cnt2[25]" as buffer
    Info: Detected ripple clock "cnt2[26]" as buffer
    Info: Detected ripple clock "cnt2[24]" as buffer
    Info: Detected ripple clock "cnt2[23]" as buffer
    Info: Detected ripple clock "cnt2[22]" as buffer
    Info: Detected ripple clock "cnt2[21]" as buffer
    Info: Detected ripple clock "cnt2[20]" as buffer

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