mux_eoc.tdf

大量VHDL写的数字系统设计有用实例达到

--lpm_mux CASCADE_CHAIN="IGNORE" DEVICE_FAMILY="Stratix II" IGNORE_CASCADE_BUFFERS="ON" LPM_SIZE=128 LPM_WIDTH=1 LPM_WIDTHS=7 data result sel
--VERSION_BEGIN 7.0 cbx_lpm_mux 2006:04:25:15:10:08:SJ cbx_mgl 2006:10:27:16:08:48:SJ  VERSION_END


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--synthesis_resources = lut 43 
SUBDESIGN mux_eoc
( 
	data[127..0]	:	input;
	result[0..0]	:	output;
	sel[6..0]	:	input;
) 
VARIABLE
	l1_w0_n0_mux_dataout	:	WIRE;
	l1_w0_n10_mux_dataout	:	WIRE;
	l1_w0_n11_mux_dataout	:	WIRE;
	l1_w0_n12_mux_dataout	:	WIRE;
	l1_w0_n13_mux_dataout	:	WIRE;
	l1_w0_n14_mux_dataout	:	WIRE;
	l1_w0_n15_mux_dataout	:	WIRE;
	l1_w0_n16_mux_dataout	:	WIRE;
	l1_w0_n17_mux_dataout	:	WIRE;
	l1_w0_n18_mux_dataout	:	WIRE;
	l1_w0_n19_mux_dataout	:	WIRE;
	l1_w0_n1_mux_dataout	:	WIRE;
	l1_w0_n20_mux_dataout	:	WIRE;
	l1_w0_n21_mux_dataout	:	WIRE;
	l1_w0_n22_mux_dataout	:	WIRE;
	l1_w0_n23_mux_dataout	:	WIRE;
	l1_w0_n24_mux_dataout	:	WIRE;
	l1_w0_n25_mux_dataout	:	WIRE;
	l1_w0_n26_mux_dataout	:	WIRE;
	l1_w0_n27_mux_dataout	:	WIRE;
	l1_w0_n28_mux_dataout	:	WIRE;
	l1_w0_n29_mux_dataout	:	WIRE;
	l1_w0_n2_mux_dataout	:	WIRE;
	l1_w0_n30_mux_dataout	:	WIRE;
	l1_w0_n31_mux_dataout	:	WIRE;
	l1_w0_n32_mux_dataout	:	WIRE;
	l1_w0_n33_mux_dataout	:	WIRE;
	l1_w0_n34_mux_dataout	:	WIRE;
	l1_w0_n35_mux_dataout	:	WIRE;
	l1_w0_n36_mux_dataout	:	WIRE;
	l1_w0_n37_mux_dataout	:	WIRE;
	l1_w0_n38_mux_dataout	:	WIRE;
	l1_w0_n39_mux_dataout	:	WIRE;
	l1_w0_n3_mux_dataout	:	WIRE;
	l1_w0_n40_mux_dataout	:	WIRE;
	l1_w0_n41_mux_dataout	:	WIRE;
	l1_w0_n42_mux_dataout	:	WIRE;
	l1_w0_n43_mux_dataout	:	WIRE;
	l1_w0_n44_mux_dataout	:	WIRE;
	l1_w0_n45_mux_dataout	:	WIRE;
	l1_w0_n46_mux_dataout	:	WIRE;
	l1_w0_n47_mux_dataout	:	WIRE;
	l1_w0_n48_mux_dataout	:	WIRE;
	l1_w0_n49_mux_dataout	:	WIRE;
	l1_w0_n4_mux_dataout	:	WIRE;
	l1_w0_n50_mux_dataout	:	WIRE;
	l1_w0_n51_mux_dataout	:	WIRE;
	l1_w0_n52_mux_dataout	:	WIRE;
	l1_w0_n53_mux_dataout	:	WIRE;
	l1_w0_n54_mux_dataout	:	WIRE;
	l1_w0_n55_mux_dataout	:	WIRE;
	l1_w0_n56_mux_dataout	:	WIRE;
	l1_w0_n57_mux_dataout	:	WIRE;
	l1_w0_n58_mux_dataout	:	WIRE;
	l1_w0_n59_mux_dataout	:	WIRE;
	l1_w0_n5_mux_dataout	:	WIRE;
	l1_w0_n60_mux_dataout	:	WIRE;
	l1_w0_n61_mux_dataout	:	WIRE;
	l1_w0_n62_mux_dataout	:	WIRE;
	l1_w0_n63_mux_dataout	:	WIRE;
	l1_w0_n6_mux_dataout	:	WIRE;
	l1_w0_n7_mux_dataout	:	WIRE;
	l1_w0_n8_mux_dataout	:	WIRE;
	l1_w0_n9_mux_dataout	:	WIRE;
	l2_w0_n0_mux_dataout	:	WIRE;
	l2_w0_n10_mux_dataout	:	WIRE;
	l2_w0_n11_mux_dataout	:	WIRE;
	l2_w0_n12_mux_dataout	:	WIRE;
	l2_w0_n13_mux_dataout	:	WIRE;
	l2_w0_n14_mux_dataout	:	WIRE;
	l2_w0_n15_mux_dataout	:	WIRE;
	l2_w0_n16_mux_dataout	:	WIRE;
	l2_w0_n17_mux_dataout	:	WIRE;
	l2_w0_n18_mux_dataout	:	WIRE;
	l2_w0_n19_mux_dataout	:	WIRE;
	l2_w0_n1_mux_dataout	:	WIRE;
	l2_w0_n20_mux_dataout	:	WIRE;
	l2_w0_n21_mux_dataout	:	WIRE;
	l2_w0_n22_mux_dataout	:	WIRE;
	l2_w0_n23_mux_dataout	:	WIRE;
	l2_w0_n24_mux_dataout	:	WIRE;
	l2_w0_n25_mux_dataout	:	WIRE;
	l2_w0_n26_mux_dataout	:	WIRE;
	l2_w0_n27_mux_dataout	:	WIRE;
	l2_w0_n28_mux_dataout	:	WIRE;
	l2_w0_n29_mux_dataout	:	WIRE;
	l2_w0_n2_mux_dataout	:	WIRE;
	l2_w0_n30_mux_dataout	:	WIRE;
	l2_w0_n31_mux_dataout	:	WIRE;
	l2_w0_n3_mux_dataout	:	WIRE;
	l2_w0_n4_mux_dataout	:	WIRE;
	l2_w0_n5_mux_dataout	:	WIRE;
	l2_w0_n6_mux_dataout	:	WIRE;
	l2_w0_n7_mux_dataout	:	WIRE;
	l2_w0_n8_mux_dataout	:	WIRE;
	l2_w0_n9_mux_dataout	:	WIRE;
	l3_w0_n0_mux_dataout	:	WIRE;
	l3_w0_n10_mux_dataout	:	WIRE;
	l3_w0_n11_mux_dataout	:	WIRE;
	l3_w0_n12_mux_dataout	:	WIRE;
	l3_w0_n13_mux_dataout	:	WIRE;
	l3_w0_n14_mux_dataout	:	WIRE;
	l3_w0_n15_mux_dataout	:	WIRE;
	l3_w0_n1_mux_dataout	:	WIRE;
	l3_w0_n2_mux_dataout	:	WIRE;
	l3_w0_n3_mux_dataout	:	WIRE;
	l3_w0_n4_mux_dataout	:	WIRE;
	l3_w0_n5_mux_dataout	:	WIRE;
	l3_w0_n6_mux_dataout	:	WIRE;
	l3_w0_n7_mux_dataout	:	WIRE;
	l3_w0_n8_mux_dataout	:	WIRE;
	l3_w0_n9_mux_dataout	:	WIRE;
	l4_w0_n0_mux_dataout	:	WIRE;
	l4_w0_n1_mux_dataout	:	WIRE;
	l4_w0_n2_mux_dataout	:	WIRE;
	l4_w0_n3_mux_dataout	:	WIRE;
	l4_w0_n4_mux_dataout	:	WIRE;
	l4_w0_n5_mux_dataout	:	WIRE;