nco_ip.tan.rpt

大量VHDL写的数字系统设计有用实例达到

; Worst-case th                                  ; N/A   ; None          ; 1.393 ns                                       ; altera_internal_jtag~TDIUTAP                               ; pzdyqx:nabboc|PZMU7345:HHRH5434|ATKJ2101[12]                         ; --                              ; altera_internal_jtag~CLKDRUSER  ; 0            ;
; Clock Setup: 'altera_internal_jtag~TCKUTAP'    ; N/A   ; None          ; 312.11 MHz ( period = 3.204 ns )               ; sld_hub:sld_hub_inst|jtag_debug_mode_usr1                  ; sld_hub:sld_hub_inst|hub_tdo~reg0                                    ; altera_internal_jtag~TCKUTAP    ; altera_internal_jtag~TCKUTAP    ; 0            ;
; Clock Setup: 'clock'                           ; N/A   ; None          ; 396.04 MHz ( period = 2.525 ns )               ; NCO:inst|NCO_st:NCO_st_inst|segment_arr_tdl:tdl|seg_rot[2] ; NCO:inst|NCO_st:NCO_st_inst|segment_sel:rot|sin_o[2]                 ; clock                           ; clock                           ; 0            ;
; Clock Setup: 'altera_internal_jtag~CLKDRUSER'  ; N/A   ; None          ; 641.03 MHz ( period = 1.560 ns )               ; pzdyqx:nabboc|VELJ8121:JDCF0099|AJQN5180[0]                ; pzdyqx:nabboc|VELJ8121:JDCF0099|AJQN5180[4]                          ; altera_internal_jtag~CLKDRUSER  ; altera_internal_jtag~CLKDRUSER  ; 0            ;
; Clock Setup: 'altera_internal_jtag~UPDATEUSER' ; N/A   ; None          ; Restricted to 816.99 MHz ( period = 1.224 ns ) ; pzdyqx:nabboc|XWDE0671[2]                                  ; pzdyqx:nabboc|XWDE0671[1]                                            ; altera_internal_jtag~UPDATEUSER ; altera_internal_jtag~UPDATEUSER ; 0            ;
; Total number of failed paths                   ;       ;               ;                                                ;                                                            ;                                                                      ;                                 ;                                 ; 0            ;
+------------------------------------------------+-------+---------------+------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------------------+---------------------------------+---------------------------------+--------------+


+--------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                           ;
+-------------------------------------------------------+--------------------+------+------------------+-------------+
; Option                                                ; Setting            ; From ; To               ; Entity Name ;
+-------------------------------------------------------+--------------------+------+------------------+-------------+
; Device Name                                           ; EP2S15F484C3       ;      ;                  ;             ;
; Timing Models                                         ; Final              ;      ;                  ;             ;
; Enables Advanced I/O Timing                           ; Off                ;      ;                  ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;                  ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;                  ;             ;
; Cut off read during write signal paths                ; On                 ;      ;                  ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;                  ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;                  ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;                  ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;                  ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;                  ;             ;
; Enable Clock Latency                                  ; Off                ;      ;                  ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;                  ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;                  ;             ;
; Number of paths to report                             ; 200                ;      ;                  ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;                  ;             ;
; Use Fast Timing Models                                ; Off                ;      ;                  ;             ;
; Report IO Paths Separately                            ; Off                ;      ;                  ;             ;
; Cut Timing Path                                       ; On                 ;      ; EPEO2888_0       ; MDCK2395    ;
; Cut Timing Path                                       ; On                 ;      ; EPEO2888_1       ; MDCK2395    ;
; Cut Timing Path                                       ; On                 ;      ; EPEO2888_2       ; MDCK2395    ;
; Cut Timing Path                                       ; On                 ;      ; EPEO2888_3       ; MDCK2395    ;
; Cut Timing Path                                       ; On                 ;      ; EPEO2888_4       ; MDCK2395    ;
; Cut Timing Path                                       ; On                 ;      ; EPEO2888_5       ; MDCK2395    ;
; Cut Timing Path                                       ; On                 ;      ; EPEO2888_6       ; MDCK2395    ;
; Cut Timing Path                                       ; On                 ;      ; EPEO2888_7       ; MDCK2395    ;
; Cut Timing Path                                       ; On                 ;      ; lcell:LJMV0916_0 ; MDCK2395    ;
; Cut Timing Path                                       ; On                 ;      ; lcell:WCRO7487_0 ; MDCK2395    ;
+-------------------------------------------------------+--------------------+------+------------------+-------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                                             ;
+---------------------------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name                 ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+---------------------------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; altera_internal_jtag~CLKDRUSER  ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;