nco_ip.fit.smsg

大量VHDL写的数字系统设计有用实例达到

        Info: Destination node NCO:inst|NCO_st:NCO_st_inst|asj_nco_mob_rw:ux123|data_out[6]
        Info: Destination node NCO:inst|NCO_st:NCO_st_inst|asj_nco_mob_rw:ux123|data_out[5]
        Info: Non-global destination nodes limited to 10 nodes
Info: Automatically promoted node sld_hub:sld_hub_inst|CLR_SIGNAL 
    Info: Automatically promoted destinations to use location or clock signal Global Clock
    Info: Following destination nodes may be non-global or may not use global or regional clocks
        Info: Destination node sld_hub:sld_hub_inst|CLR_SIGNAL~_wirecell
Info: Automatically promoted node sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[0] 
    Info: Automatically promoted destinations to use location or clock signal Global Clock
    Info: Following destination nodes may be non-global or may not use global or regional clocks
        Info: Destination node sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~398
        Info: Destination node sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~5
        Info: Destination node sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[0]~_wirecell
Info: Automatically promoted node pzdyqx:nabboc|VELJ8121:JDCF0099|EHEH8502 
    Info: Automatically promoted destinations to use location or clock signal Global Clock
Info: Automatically promoted node pzdyqx:nabboc|process1~0 
    Info: Automatically promoted destinations to use location or clock signal Global Clock
Info: Starting register packing
Info: Finished register packing: elapsed time is 00:00:00
    Extra Info: No registers were packed into other blocks
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
    Info: Number of I/O pins in group: 54 (unused VREF, 3.30 VCCIO, 33 input, 21 output, 0 bidirectional)
        Info: I/O standards used: 3.3-V LVTTL.
Info: I/O bank details before I/O pin placement
    Info: Statistics of I/O banks
        Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  39 pins available
        Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  43 pins available
        Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  49 pins available
        Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  35 pins available
        Info: I/O bank number 5 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  44 pins available
        Info: I/O bank number 6 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  40 pins available
        Info: I/O bank number 7 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  34 pins available
        Info: I/O bank number 8 does not use VREF pins and has unused VCCIO pins. 4 total pin(s) used --  43 pins available
        Info: I/O bank number 9 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  6 pins available
        Info: I/O bank number 10 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  6 pins available
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:01
Info: Estimated most critical path is register to register delay of 2.689 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X17_Y10; Fanout = 7; REG Node = 'sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[8]'
    Info: 2: + IC(0.619 ns) + CELL(0.357 ns) = 0.976 ns; Loc. = LAB_X19_Y9; Fanout = 7; COMB Node = 'sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|clear_signal~22'
    Info: 3: + IC(0.129 ns) + CELL(0.272 ns) = 1.377 ns; Loc. = LAB_X19_Y9; Fanout = 5; COMB Node = 'sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|word_counter[0]~360'
    Info: 4: + IC(0.566 ns) + CELL(0.746 ns) = 2.689 ns; Loc. = LAB_X15_Y9; Fanout = 6; REG Node = 'sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|word_counter[1]'
    Info: Total cell delay = 1.375 ns ( 51.13 % )
    Info: Total interconnect delay = 1.314 ns ( 48.87 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 2%
    Info: The peak interconnect region extends from location X13_Y14 to location X26_Y27
Info: Fitter routing operations ending: elapsed time is 00:00:01
Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
    Info: Optimizations that may affect the design's routability were skipped
    Info: Optimizations that may affect the design's timing were skipped
Info: Fitter merged 1 physical RAM blocks that contain multiple logical RAM slices into a single location
    Info: Following physical RAM blocks contain multiple logical RAM slices
        Info: Physical RAM block M4K_X20_Y17 contains the following logical RAM slices
            Info: RAM slice: NCO:inst|NCO_st:NCO_st_inst|asj_nco_as_m_cen:ux0120|altsyncram:altsyncram_component0|altsyncram_jl81:auto_generated|ram_block1a0
            Info: RAM slice: NCO:inst|NCO_st:NCO_st_inst|asj_nco_as_m_cen:ux0120|altsyncram:altsyncram_component0|altsyncram_jl81:auto_generated|ram_block1a1
            Info: RAM slice: NCO:inst|NCO_st:NCO_st_inst|asj_nco_as_m_cen:ux0120|altsyncram:altsyncram_component0|altsyncram_jl81:auto_generated|ram_block1a2
            Info: RAM slice: NCO:inst|NCO_st:NCO_st_inst|asj_nco_as_m_cen:ux0120|altsyncram:altsyncram_component0|altsyncram_jl81:auto_generated|ram_block1a3
            Info: RAM slice: NCO:inst|NCO_st:NCO_st_inst|asj_nco_as_m_cen:ux0120|altsyncram:altsyncram_component0|altsyncram_jl81:auto_generated|ram_block1a4
            Info: RAM slice: NCO:inst|NCO_st:NCO_st_inst|asj_nco_as_m_cen:ux0120|altsyncram:altsyncram_component0|altsyncram_jl81:auto_generated|ram_block1a5
            Info: RAM slice: NCO:inst|NCO_st:NCO_st_inst|asj_nco_as_m_cen:ux0120|altsyncram:altsyncram_component0|altsyncram_jl81:auto_generated|ram_block1a6
            Info: RAM slice: NCO:inst|NCO_st:NCO_st_inst|asj_nco_as_m_cen:ux0120|altsyncram:altsyncram_component0|altsyncram_jl81:auto_generated|ram_block1a7
            Info: RAM slice: NCO:inst|NCO_st:NCO_st_inst|asj_nco_as_m_cen:ux0120|altsyncram:altsyncram_component0|altsyncram_jl81:auto_generated|ram_block1a8
            Info: RAM slice: NCO:inst|NCO_st:NCO_st_inst|asj_nco_as_m_cen:ux0121|altsyncram:altsyncram_component0|altsyncram_el81:auto_generated|ram_block1a0
            Info: RAM slice: NCO:inst|NCO_st:NCO_st_inst|asj_nco_as_m_cen:ux0121|altsyncram:altsyncram_component0|altsyncram_el81:auto_generated|ram_block1a1
            Info: RAM slice: NCO:inst|NCO_st:NCO_st_inst|asj_nco_as_m_cen:ux0121|altsyncram:altsyncram_component0|altsyncram_el81:auto_generated|ram_block1a2
            Info: RAM slice: NCO:inst|NCO_st:NCO_st_inst|asj_nco_as_m_cen:ux0121|altsyncram:altsyncram_component0|altsyncram_el81:auto_generated|ram_block1a3
            Info: RAM slice: NCO:inst|NCO_st:NCO_st_inst|asj_nco_as_m_cen:ux0121|altsyncram:altsyncram_component0|altsyncram_el81:auto_generated|ram_block1a4
            Info: RAM slice: NCO:inst|NCO_st:NCO_st_inst|asj_nco_as_m_cen:ux0121|altsyncram:altsyncram_component0|altsyncram_el81:auto_generated|ram_block1a5
            Info: RAM slice: NCO:inst|NCO_st:NCO_st_inst|asj_nco_as_m_cen:ux0121|altsyncram:altsyncram_component0|altsyncram_el81:auto_generated|ram_block1a6
            Info: RAM slice: NCO:inst|NCO_st:NCO_st_inst|asj_nco_as_m_cen:ux0121|altsyncram:altsyncram_component0|altsyncram_el81:auto_generated|ram_block1a7
            Info: RAM slice: NCO:inst|NCO_st:NCO_st_inst|asj_nco_as_m_cen:ux0121|altsyncram:altsyncram_component0|altsyncram_el81:auto_generated|ram_block1a8
Info: Started post-fitting delay annotation
Warning: Found 21 output pins without output pin load capacitance assignment
    Info: Pin "out_valid" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "fcos_o[9]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "fcos_o[8]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "fcos_o[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "fcos_o[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "fcos_o[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "fcos_o[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "fcos_o[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "fcos_o[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "fcos_o[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "fcos_o[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "fsin_o[9]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "fsin_o[8]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "fsin_o[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "fsin_o[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "fsin_o[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "fsin_o[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "fsin_o[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "fsin_o[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "fsin_o[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "fsin_o[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Delay annotation completed successfully
Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Info: Quartus II Fitter was successful. 0 errors, 3 warnings
    Info: Allocated 209 megabytes of memory during processing
    Info: Processing ended: Sun Apr 29 10:21:36 2007
    Info: Elapsed time: 00:00:23