scan_led.tan.rpt

大量VHDL写的数字系统设计有用实例达到

; N/A   ; None         ; 10.504 ns  ; cnt8[1] ; seg[3]  ; clk        ;
; N/A   ; None         ; 10.259 ns  ; cnt8[1] ; seg[7]  ; clk        ;
; N/A   ; None         ; 10.241 ns  ; cnt8[0] ; seg[3]  ; clk        ;
; N/A   ; None         ; 10.232 ns  ; cnt8[1] ; scan[3] ; clk        ;
; N/A   ; None         ; 10.065 ns  ; cnt8[1] ; scan[1] ; clk        ;
; N/A   ; None         ; 10.013 ns  ; cnt8[1] ; scan[0] ; clk        ;
; N/A   ; None         ; 9.980 ns   ; cnt8[0] ; seg[7]  ; clk        ;
; N/A   ; None         ; 9.953 ns   ; cnt8[0] ; scan[3] ; clk        ;
; N/A   ; None         ; 9.895 ns   ; cnt8[0] ; seg[6]  ; clk        ;
; N/A   ; None         ; 9.873 ns   ; cnt8[0] ; scan[1] ; clk        ;
; N/A   ; None         ; 9.821 ns   ; cnt8[1] ; scan[4] ; clk        ;
; N/A   ; None         ; 9.818 ns   ; cnt8[0] ; scan[0] ; clk        ;
; N/A   ; None         ; 9.780 ns   ; cnt8[0] ; seg[1]  ; clk        ;
; N/A   ; None         ; 9.721 ns   ; cnt8[2] ; seg[3]  ; clk        ;
; N/A   ; None         ; 9.684 ns   ; cnt8[0] ; scan[4] ; clk        ;
; N/A   ; None         ; 9.674 ns   ; cnt8[1] ; seg[4]  ; clk        ;
; N/A   ; None         ; 9.582 ns   ; cnt8[1] ; scan[5] ; clk        ;
; N/A   ; None         ; 9.507 ns   ; cnt8[1] ; seg[5]  ; clk        ;
; N/A   ; None         ; 9.499 ns   ; cnt8[1] ; seg[6]  ; clk        ;
; N/A   ; None         ; 9.495 ns   ; cnt8[1] ; scan[6] ; clk        ;
; N/A   ; None         ; 9.488 ns   ; cnt8[2] ; seg[7]  ; clk        ;
; N/A   ; None         ; 9.457 ns   ; cnt8[2] ; scan[3] ; clk        ;
; N/A   ; None         ; 9.429 ns   ; cnt8[0] ; scan[5] ; clk        ;
; N/A   ; None         ; 9.425 ns   ; cnt8[1] ; seg[1]  ; clk        ;
; N/A   ; None         ; 9.396 ns   ; cnt8[0] ; seg[4]  ; clk        ;
; N/A   ; None         ; 9.365 ns   ; cnt8[2] ; scan[1] ; clk        ;
; N/A   ; None         ; 9.345 ns   ; cnt8[1] ; seg[2]  ; clk        ;
; N/A   ; None         ; 9.322 ns   ; cnt8[2] ; scan[0] ; clk        ;
; N/A   ; None         ; 9.279 ns   ; cnt8[0] ; seg[5]  ; clk        ;
; N/A   ; None         ; 9.262 ns   ; cnt8[0] ; scan[6] ; clk        ;
; N/A   ; None         ; 9.171 ns   ; cnt8[2] ; scan[4] ; clk        ;
; N/A   ; None         ; 9.136 ns   ; cnt8[1] ; scan[2] ; clk        ;
; N/A   ; None         ; 9.118 ns   ; cnt8[1] ; scan[7] ; clk        ;
; N/A   ; None         ; 9.078 ns   ; cnt8[0] ; seg[2]  ; clk        ;
; N/A   ; None         ; 8.923 ns   ; cnt8[2] ; scan[5] ; clk        ;
; N/A   ; None         ; 8.904 ns   ; cnt8[2] ; seg[4]  ; clk        ;
; N/A   ; None         ; 8.882 ns   ; cnt8[0] ; scan[7] ; clk        ;
; N/A   ; None         ; 8.865 ns   ; cnt8[0] ; scan[2] ; clk        ;
; N/A   ; None         ; 8.771 ns   ; cnt8[2] ; scan[6] ; clk        ;
; N/A   ; None         ; 8.766 ns   ; cnt8[2] ; seg[5]  ; clk        ;
; N/A   ; None         ; 8.574 ns   ; cnt8[2] ; seg[2]  ; clk        ;
; N/A   ; None         ; 8.382 ns   ; cnt8[2] ; scan[7] ; clk        ;
; N/A   ; None         ; 8.355 ns   ; cnt8[2] ; scan[2] ; clk        ;
+-------+--------------+------------+---------+---------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Sat Apr 07 11:05:27 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off scan_led -c scan_led --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 340.02 MHz between source register "cnt8[0]" and destination register "cnt8[2]"
    Info: fmax restricted to clock pin edge rate 2.941 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.191 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X19_Y6_N27; Fanout = 18; REG Node = 'cnt8[0]'
            Info: 2: + IC(0.459 ns) + CELL(0.624 ns) = 1.083 ns; Loc. = LCCOMB_X19_Y6_N2; Fanout = 1; COMB Node = 'cnt8[2]~65'
            Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 1.191 ns; Loc. = LCFF_X19_Y6_N3; Fanout = 14; REG Node = 'cnt8[2]'
            Info: Total cell delay = 0.732 ns ( 61.46 % )
            Info: Total interconnect delay = 0.459 ns ( 38.54 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 2.790 ns
                Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 3; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(0.895 ns) + CELL(0.666 ns) = 2.790 ns; Loc. = LCFF_X19_Y6_N3; Fanout = 14; REG Node = 'cnt8[2]'
                Info: Total cell delay = 1.756 ns ( 62.94 % )
                Info: Total interconnect delay = 1.034 ns ( 37.06 % )
            Info: - Longest clock path from clock "clk" to source register is 2.790 ns
                Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 3; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(0.895 ns) + CELL(0.666 ns) = 2.790 ns; Loc. = LCFF_X19_Y6_N27; Fanout = 18; REG Node = 'cnt8[0]'
                Info: Total cell delay = 1.756 ns ( 62.94 % )
                Info: Total interconnect delay = 1.034 ns ( 37.06 % )
        Info: + Micro clock to output delay of source is 0.304 ns
        Info: + Micro setup delay of destination is -0.040 ns
Info: tco from clock "clk" to destination pin "seg[3]" through register "cnt8[1]" is 10.504 ns
    Info: + Longest clock path from clock "clk" to source register is 2.790 ns
        Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 3; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.895 ns) + CELL(0.666 ns) = 2.790 ns; Loc. = LCFF_X19_Y6_N13; Fanout = 17; REG Node = 'cnt8[1]'
        Info: Total cell delay = 1.756 ns ( 62.94 % )
        Info: Total interconnect delay = 1.034 ns ( 37.06 % )
    Info: + Micro clock to output delay of source is 0.304 ns
    Info: + Longest register to pin delay is 7.410 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X19_Y6_N13; Fanout = 17; REG Node = 'cnt8[1]'
        Info: 2: + IC(0.883 ns) + CELL(0.624 ns) = 1.507 ns; Loc. = LCCOMB_X19_Y6_N0; Fanout = 1; COMB Node = 'Mux16~56'
        Info: 3: + IC(2.847 ns) + CELL(3.056 ns) = 7.410 ns; Loc. = PIN_25; Fanout = 0; PIN Node = 'seg[3]'
        Info: Total cell delay = 3.680 ns ( 49.66 % )
        Info: Total interconnect delay = 3.730 ns ( 50.34 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 101 megabytes of memory during processing
    Info: Processing ended: Sat Apr 07 11:05:27 2007
    Info: Elapsed time: 00:00:00