📄 shop.tan.qmsg
字号:
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" { } { { "shop.vhd" "" { Text "D:/my_eda2/shop/shop.vhd" 10 -1 0 } } { "e:/altera/quartus ii7.0/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus ii7.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "set " "Info: Assuming node \"set\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." { } { { "shop.vhd" "" { Text "D:/my_eda2/shop/shop.vhd" 11 -1 0 } } } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0} } { } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "clk1khz " "Info: Detected ripple clock \"clk1khz\" as buffer" { } { { "shop.vhd" "" { Text "D:/my_eda2/shop/shop.vhd" 22 -1 0 } } { "e:/altera/quartus ii7.0/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus ii7.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk1khz" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "\\process8:cnt\[0\] " "Info: Detected ripple clock \"\\process8:cnt\[0\]\" as buffer" { } { { "e:/altera/quartus ii7.0/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus ii7.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "\\process8:cnt\[0\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} } { } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register item\[1\] register qua\[0\] 126.14 MHz 7.928 ns Internal " "Info: Clock \"clk\" has Internal fmax of 126.14 MHz between source register \"item\[1\]\" and destination register \"qua\[0\]\" (period= 7.928 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.669 ns + Longest register register " "Info: + Longest register to register delay is 7.669 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns item\[1\] 1 REG LCFF_X13_Y9_N15 119 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X13_Y9_N15; Fanout = 119; REG Node = 'item\[1\]'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { item[1] } "NODE_NAME" } } { "shop.vhd" "" { Text "D:/my_eda2/shop/shop.vhd" 52 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.629 ns) 4.629 ns ram\[2\]\[0\]~7109 2 COMB LOOP LCCOMB_X17_Y8_N0 2 " "Info: 2: + IC(0.000 ns) + CELL(4.629 ns) = 4.629 ns; Loc. = LCCOMB_X17_Y8_N0; Fanout = 2; COMB LOOP Node = 'ram\[2\]\[0\]~7109'" { { "Info" "ITDB_PART_OF_SCC" "ram\[2\]\[0\]~7109 LCCOMB_X17_Y8_N0 " "Info: Loc. = LCCOMB_X17_Y8_N0; Node \"ram\[2\]\[0\]~7109\"" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { ram[2][0]~7109 } "NODE_NAME" } } } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0} { "Info" "ITDB_PART_OF_SCC" "ram~7108 LCCOMB_X18_Y6_N4 " "Info: Loc. = LCCOMB_X18_Y6_N4; Node \"ram~7108\"" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { ram~7108 } "NODE_NAME" } } } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0} } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { ram[2][0]~7109 } "NODE_NAME" } } { "shop.vhd" "" { Text "D:/my_eda2/shop/shop.vhd" 52 -1 0 } } { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { ram~7108 } "NODE_NAME" } } { "shop.vhd" "" { Text "D:/my_eda2/shop/shop.vhd" 21 -1 0 } } { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "4.629 ns" { item[1] ram[2][0]~7109 } "NODE_NAME" } } { "shop.vhd" "" { Text "D:/my_eda2/shop/shop.vhd" 52 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.053 ns) + CELL(0.206 ns) 5.888 ns qua~206 3 COMB LCCOMB_X14_Y9_N0 1 " "Info: 3: + IC(1.053 ns) + CELL(0.206 ns) = 5.888 ns; Loc. = LCCOMB_X14_Y9_N0; Fanout = 1; COMB Node = 'qua~206'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.259 ns" { ram[2][0]~7109 qua~206 } "NODE_NAME" } } { "shop.vhd" "" { Text "D:/my_eda2/shop/shop.vhd" 25 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.467 ns) + CELL(0.206 ns) 7.561 ns qua\[0\]~141 4 COMB LCCOMB_X18_Y6_N2 1 " "Info: 4: + IC(1.467 ns) + CELL(0.206 ns) = 7.561 ns; Loc. = LCCOMB_X18_Y6_N2; Fanout = 1; COMB Node = 'qua\[0\]~141'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.673 ns" { qua~206 qua[0]~141 } "NODE_NAME" } } { "shop.vhd" "" { Text "D:/my_eda2/shop/shop.vhd" 52 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 7.669 ns qua\[0\] 5 REG LCFF_X18_Y6_N3 17 " "Info: 5: + IC(0.000 ns) + CELL(0.108 ns) = 7.669 ns; Loc. = LCFF_X18_Y6_N3; Fanout = 17; REG Node = 'qua\[0\]'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { qua[0]~141 qua[0] } "NODE_NAME" } } { "shop.vhd" "" { Text "D:/my_eda2/shop/shop.vhd" 52 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.149 ns ( 67.14 % ) " "Info: Total cell delay = 5.149 ns ( 67.14 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.520 ns ( 32.86 % ) " "Info: Total interconnect delay = 2.520 ns ( 32.86 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "7.669 ns" { item[1] ram[2][0]~7109 qua~206 qua[0]~141 qua[0] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "7.669 ns" { item[1] ram[2][0]~7109 qua~206 qua[0]~141 qua[0] } { 0.000ns 0.000ns 1.053ns 1.467ns 0.000ns } { 0.000ns 4.629ns 0.206ns 0.206ns 0.108ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.005 ns - Smallest " "Info: - Smallest clock skew is 0.005 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 8.574 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 8.574 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "shop.vhd" "" { Text "D:/my_eda2/shop/shop.vhd" 10 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.522 ns) + CELL(0.970 ns) 2.582 ns clk1khz 2 REG LCFF_X1_Y9_N29 2 " "Info: 2: + IC(0.522 ns) + CELL(0.970 ns) = 2.582 ns; Loc. = LCFF_X1_Y9_N29; Fanout = 2; REG Node = 'clk1khz'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.492 ns" { clk clk1khz } "NODE_NAME" } } { "shop.vhd" "" { Text "D:/my_eda2/shop/shop.vhd" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.805 ns) + CELL(0.000 ns) 3.387 ns clk1khz~clkctrl 3 COMB CLKCTRL_G0 2 " "Info: 3: + IC(0.805 ns) + CELL(0.000 ns) = 3.387 ns; Loc. = CLKCTRL_G0; Fanout = 2; COMB Node = 'clk1khz~clkctrl'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.805 ns" { clk1khz clk1khz~clkctrl } "NODE_NAME" } } { "shop.vhd" "" { Text "D:/my_eda2/shop/shop.vhd" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.907 ns) + CELL(0.970 ns) 5.264 ns \\process8:cnt\[0\] 4 REG LCFF_X15_Y8_N1 12 " "Info: 4: + IC(0.907 ns) + CELL(0.970 ns) = 5.264 ns; Loc. = LCFF_X15_Y8_N1; Fanout = 12; REG Node = '\\process8:cnt\[0\]'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.877 ns" { clk1khz~clkctrl \process8:cnt[0] } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.751 ns) + CELL(0.000 ns) 7.015 ns \\process8:cnt\[0\]~clkctrl 5 COMB CLKCTRL_G3 52 " "Info: 5: + IC(1.751 ns) + CELL(0.000 ns) = 7.015 ns; Loc. = CLKCTRL_G3; Fanout = 52; COMB Node = '\\process8:cnt\[0\]~clkctrl'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.751 ns" { \process8:cnt[0] \process8:cnt[0]~clkctrl } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.893 ns) + CELL(0.666 ns) 8.574 ns qua\[0\] 6 REG LCFF_X18_Y6_N3 17 " "Info: 6: + IC(0.893 ns) + CELL(0.666 ns) = 8.574 ns; Loc. = LCFF_X18_Y6_N3; Fanout = 17; REG Node = 'qua\[0\]'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.559 ns" { \process8:cnt[0]~clkctrl qua[0] } "NODE_NAME" } } { "shop.vhd" "" { Text "D:/my_eda2/shop/shop.vhd" 52 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.696 ns ( 43.11 % ) " "Info: Total cell delay = 3.696 ns ( 43.11 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.878 ns ( 56.89 % ) " "Info: Total interconnect delay = 4.878 ns ( 56.89 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "8.574 ns" { clk clk1khz clk1khz~clkctrl \process8:cnt[0] \process8:cnt[0]~clkctrl qua[0] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "8.574 ns" { clk clk~combout clk1khz clk1khz~clkctrl \process8:cnt[0] \process8:cnt[0]~clkctrl qua[0] } { 0.000ns 0.000ns 0.522ns 0.805ns 0.907ns 1.751ns 0.893ns } { 0.000ns 1.090ns 0.970ns 0.000ns 0.970ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 8.569 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 8.569 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "shop.vhd" "" { Text "D:/my_eda2/shop/shop.vhd" 10 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.522 ns) + CELL(0.970 ns) 2.582 ns clk1khz 2 REG LCFF_X1_Y9_N29 2 " "Info: 2: + IC(0.522 ns) + CELL(0.970 ns) = 2.582 ns; Loc. = LCFF_X1_Y9_N29; Fanout = 2; REG Node = 'clk1khz'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.492 ns" { clk clk1khz } "NODE_NAME" } } { "shop.vhd" "" { Text "D:/my_eda2/shop/shop.vhd" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.805 ns) + CELL(0.000 ns) 3.387 ns clk1khz~clkctrl 3 COMB CLKCTRL_G0 2 " "Info: 3: + IC(0.805 ns) + CELL(0.000 ns) = 3.387 ns; Loc. = CLKCTRL_G0; Fanout = 2; COMB Node = 'clk1khz~clkctrl'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.805 ns" { clk1khz clk1khz~clkctrl } "NODE_NAME" } } { "shop.vhd" "" { Text "D:/my_eda2/shop/shop.vhd" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.907 ns) + CELL(0.970 ns) 5.264 ns \\process8:cnt\[0\] 4 REG LCFF_X15_Y8_N1 12 " "Info: 4: + IC(0.907 ns) + CELL(0.970 ns) = 5.264 ns; Loc. = LCFF_X15_Y8_N1; Fanout = 12; REG Node = '\\process8:cnt\[0\]'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.877 ns" { clk1khz~clkctrl \process8:cnt[0] } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.751 ns) + CELL(0.000 ns) 7.015 ns \\process8:cnt\[0\]~clkctrl 5 COMB CLKCTRL_G3 52 " "Info: 5: + IC(1.751 ns) + CELL(0.000 ns) = 7.015 ns; Loc. = CLKCTRL_G3; Fanout = 52; COMB Node = '\\process8:cnt\[0\]~clkctrl'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.751 ns" { \process8:cnt[0] \process8:cnt[0]~clkctrl } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.888 ns) + CELL(0.666 ns) 8.569 ns item\[1\] 6 REG LCFF_X13_Y9_N15 119 " "Info: 6: + IC(0.888 ns) + CELL(0.666 ns) = 8.569 ns; Loc. = LCFF_X13_Y9_N15; Fanout = 119; REG Node = 'item\[1\]'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.554 ns" { \process8:cnt[0]~clkctrl item[1] } "NODE_NAME" } } { "shop.vhd" "" { Text "D:/my_eda2/shop/shop.vhd" 52 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.696 ns ( 43.13 % ) " "Info: Total cell delay = 3.696 ns ( 43.13 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.873 ns ( 56.87 % ) " "Info: Total interconnect delay = 4.873 ns ( 56.87 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "8.569 ns" { clk clk1khz clk1khz~clkctrl \process8:cnt[0] \process8:cnt[0]~clkctrl item[1] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "8.569 ns" { clk clk~combout clk1khz clk1khz~clkctrl \process8:cnt[0] \process8:cnt[0]~clkctrl item[1] } { 0.000ns 0.000ns 0.522ns 0.805ns 0.907ns 1.751ns 0.888ns } { 0.000ns 1.090ns 0.970ns 0.000ns 0.970ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "8.574 ns" { clk clk1khz clk1khz~clkctrl \process8:cnt[0] \process8:cnt[0]~clkctrl qua[0] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "8.574 ns" { clk clk~combout clk1khz clk1khz~clkctrl \process8:cnt[0] \process8:cnt[0]~clkctrl qua[0] } { 0.000ns 0.000ns 0.522ns 0.805ns 0.907ns 1.751ns 0.893ns } { 0.000ns 1.090ns 0.970ns 0.000ns 0.970ns 0.000ns 0.666ns } "" } } { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "8.569 ns" { clk clk1khz clk1khz~clkctrl \process8:cnt[0] \process8:cnt[0]~clkctrl item[1] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "8.569 ns" { clk clk~combout clk1khz clk1khz~clkctrl \process8:cnt[0] \process8:cnt[0]~clkctrl item[1] } { 0.000ns 0.000ns 0.522ns 0.805ns 0.907ns 1.751ns 0.888ns } { 0.000ns 1.090ns 0.970ns 0.000ns 0.970ns 0.000ns 0.666ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" { } { { "shop.vhd" "" { Text "D:/my_eda2/shop/shop.vhd" 52 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" { } { { "shop.vhd" "" { Text "D:/my_eda2/shop/shop.vhd" 52 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "7.669 ns" { item[1] ram[2][0]~7109 qua~206 qua[0]~141 qua[0] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "7.669 ns" { item[1] ram[2][0]~7109 qua~206 qua[0]~141 qua[0] } { 0.000ns 0.000ns 1.053ns 1.467ns 0.000ns } { 0.000ns 4.629ns 0.206ns 0.206ns 0.108ns } "" } } { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "8.574 ns" { clk clk1khz clk1khz~clkctrl \process8:cnt[0] \process8:cnt[0]~clkctrl qua[0] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "8.574 ns" { clk clk~combout clk1khz clk1khz~clkctrl \process8:cnt[0] \process8:cnt[0]~clkctrl qua[0] } { 0.000ns 0.000ns 0.522ns 0.805ns 0.907ns 1.751ns 0.893ns } { 0.000ns 1.090ns 0.970ns 0.000ns 0.970ns 0.000ns 0.666ns } "" } } { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "8.569 ns" { clk clk1khz clk1khz~clkctrl \process8:cnt[0] \process8:cnt[0]~clkctrl item[1] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "8.569 ns" { clk clk~combout clk1khz clk1khz~clkctrl \process8:cnt[0] \process8:cnt[0]~clkctrl item[1] } { 0.000ns 0.000ns 0.522ns 0.805ns 0.907ns 1.751ns 0.888ns } { 0.000ns 1.090ns 0.970ns 0.000ns 0.970ns 0.000ns 0.666ns } "" } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "set register ram\[1\]\[7\]~1977 register ram\[1\]\[7\]~1977 172.5 MHz 5.797 ns Internal " "Info: Clock \"set\" has Internal fmax of 172.5 MHz between source register \"ram\[1\]\[7\]~1977\" and destination register \"ram\[1\]\[7\]~1977\" (period= 5.797 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.831 ns + Longest register register " "Info: + Longest register to register delay is 4.831 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ram\[1\]\[7\]~1977 1 REG LCCOMB_X17_Y8_N14 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCCOMB_X17_Y8_N14; Fanout = 4; REG Node = 'ram\[1\]\[7\]~1977'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { ram[1][7]~1977 } "NODE_NAME" } } { "shop.vhd" "" { Text "D:/my_eda2/shop/shop.vhd" 52 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.826 ns) 3.826 ns ram~7164 2 COMB LOOP LCCOMB_X17_Y8_N18 2 " "Info: 2: + IC(0.000 ns) + CELL(3.826 ns) = 3.826 ns; Loc. = LCCOMB_X17_Y8_N18; Fanout = 2; COMB LOOP Node = 'ram~7164'" { { "Info" "ITDB_PART_OF_SCC" "ram~7164 LCCOMB_X17_Y8_N18 " "Info: Loc. = LCCOMB_X17_Y8_N18; Node \"ram~7164\"" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { ram~7164 } "NODE_NAME" } } } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0} { "Info" "ITDB_PART_OF_SCC" "ram\[1\]\[7\]~7165 LCCOMB_X17_Y9_N18 " "Info: Loc. = LCCOMB_X17_Y9_N18; Node \"ram\[1\]\[7\]~7165\"" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { ram[1][7]~7165 } "NODE_NAME" } } } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0} } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { ram~7164 } "NODE_NAME" } } { "shop.vhd" "" { Text "D:/my_eda2/shop/shop.vhd" 21 -1 0 } } { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { ram[1][7]~7165 } "NODE_NAME" } } { "shop.vhd" "" { Text "D:/my_eda2/shop/shop.vhd" 52 -1 0 } } { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "3.826 ns" { ram[1][7]~1977 ram~7164 } "NODE_NAME" } } { "shop.vhd" "" { Text "D:/my_eda2/shop/shop.vhd" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.381 ns) + CELL(0.624 ns) 4.831 ns ram\[1\]\[7\]~1977 3 REG LCCOMB_X17_Y8_N14 4 " "Info: 3: + IC(0.381 ns) + CELL(0.624 ns) = 4.831 ns; Loc. = LCCOMB_X17_Y8_N14; Fanout = 4; REG Node = 'ram\[1\]\[7\]~1977'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.005 ns" { ram~7164 ram[1][7]~1977 } "NODE_NAME" } } { "shop.vhd" "" { Text "D:/my_eda2/shop/shop.vhd" 52 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.450 ns ( 92.11 % ) " "Info: Total cell delay = 4.450 ns ( 92.11 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.381 ns ( 7.89 % ) " "Info: Total interconnect delay = 0.381 ns ( 7.89 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "4.831 ns" { ram[1][7]~1977 ram~7164 ram[1][7]~1977 } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "4.831 ns" { ram[1][7]~1977 ram~7164 ram[1][7]~1977 } { 0.000ns 0.000ns 0.381ns } { 0.000ns 3.826ns 0.624ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "set destination 3.662 ns + Shortest register " "Info: + Shortest clock path from clock \"set\" to destination register is 3.662 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.944 ns) 0.944 ns set 1 CLK PIN_133 172 " "Info: 1: + IC(0.000 ns) + CELL(0.944 ns) = 0.944 ns; Loc. = PIN_133; Fanout = 172; CLK Node = 'set'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { set } "NODE_NAME" } } { "shop.vhd" "" { Text "D:/my_eda2/shop/shop.vhd" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.512 ns) + CELL(0.206 ns) 3.662 ns ram\[1\]\[7\]~1977 2 REG LCCOMB_X17_Y8_N14 4 " "Info: 2: + IC(2.512 ns) + CELL(0.206 ns) = 3.662 ns; Loc. = LCCOMB_X17_Y8_N14; Fanout = 4; REG Node = 'ram\[1\]\[7\]~1977'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.718 ns" { set ram[1][7]~1977 } "NODE_NAME" } } { "shop.vhd" "" { Text "D:/my_eda2/shop/shop.vhd" 52 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.150 ns ( 31.40 % ) " "Info: Total cell delay = 1.150 ns ( 31.40 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.512 ns ( 68.60 % ) " "Info: Total interconnect delay = 2.512 ns ( 68.60 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "3.662 ns" { set ram[1][7]~1977 } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "3.662 ns" { set set~combout ram[1][7]~1977 } { 0.000ns 0.000ns 2.512ns } { 0.000ns 0.944ns 0.206ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "set source 3.662 ns - Longest register " "Info: - Longest clock path from clock \"set\" to source register is 3.662 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.944 ns) 0.944 ns set 1 CLK PIN_133 172 " "Info: 1: + IC(0.000 ns) + CELL(0.944 ns) = 0.944 ns; Loc. = PIN_133; Fanout = 172; CLK Node = 'set'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { set } "NODE_NAME" } } { "shop.vhd" "" { Text "D:/my_eda2/shop/shop.vhd" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.512 ns) + CELL(0.206 ns) 3.662 ns ram\[1\]\[7\]~1977 2 REG LCCOMB_X17_Y8_N14 4 " "Info: 2: + IC(2.512 ns) + CELL(0.206 ns) = 3.662 ns; Loc. = LCCOMB_X17_Y8_N14; Fanout = 4; REG Node = 'ram\[1\]\[7\]~1977'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.718 ns" { set ram[1][7]~1977 } "NODE_NAME" } } { "shop.vhd" "" { Text "D:/my_eda2/shop/shop.vhd" 52 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.150 ns ( 31.40 % ) " "Info: Total cell delay = 1.150 ns ( 31.40 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.512 ns ( 68.60 % ) " "Info: Total interconnect delay = 2.512 ns ( 68.60 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "3.662 ns" { set ram[1][7]~1977 } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "3.662 ns" { set set~combout ram[1][7]~1977 } { 0.000ns 0.000ns 2.512ns } { 0.000ns 0.944ns 0.206ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "3.662 ns" { set ram[1][7]~1977 } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "3.662 ns" { set set~combout ram[1][7]~1977 } { 0.000ns 0.000ns 2.512ns } { 0.000ns 0.944ns 0.206ns } "" } } { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "3.662 ns" { set ram[1][7]~1977 } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "3.662 ns" { set set~combout ram[1][7]~1977 } { 0.000ns 0.000ns 2.512ns } { 0.000ns 0.944ns 0.206ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.000 ns + " "Info: + Micro clock to output delay of source is 0.000 ns" { } { { "shop.vhd" "" { Text "D:/my_eda2/shop/shop.vhd" 52 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.966 ns + " "Info: + Micro setup delay of destination is 0.966 ns" { } { { "shop.vhd" "" { Text "D:/my_eda2/shop/shop.vhd" 52 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "4.831 ns" { ram[1][7]~1977 ram~7164 ram[1][7]~1977 } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "4.831 ns" { ram[1][7]~1977 ram~7164 ram[1][7]~1977 } { 0.000ns 0.000ns 0.381ns } { 0.000ns 3.826ns 0.624ns } "" } } { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "3.662 ns" { set ram[1][7]~1977 } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "3.662 ns" { set set~combout ram[1][7]~1977 } { 0.000ns 0.000ns 2.512ns } { 0.000ns 0.944ns 0.206ns } "" } } { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "3.662 ns" { set ram[1][7]~1977 } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "3.662 ns" { set set~combout ram[1][7]~1977 } { 0.000ns 0.000ns 2.512ns } { 0.000ns 0.944ns 0.206ns } "" } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "ram\[2\]\[6\]~1933 set set 9.929 ns register " "Info: tsu for register \"ram\[2\]\[6\]~1933\" (data pin = \"set\", clock pin = \"set\") is 9.929 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "12.088 ns + Longest pin register " "Info: + Longest pin to register delay is 12.088 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.944 ns) 0.944 ns set 1 CLK PIN_133 172 " "Info: 1: + IC(0.000 ns) + CELL(0.944 ns) = 0.944 ns; Loc. = PIN_133; Fanout = 172; CLK Node = 'set'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { set } "NODE_NAME" } } { "shop.vhd" "" { Text "D:/my_eda2/shop/shop.vhd" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(9.848 ns) 10.792 ns ram~7156 2 COMB LOOP LCCOMB_X13_Y9_N2 2 " "Info: 2: + IC(0.000 ns) + CELL(9.848 ns) = 10.792 ns; Loc. = LCCOMB_X13_Y9_N2; Fanout = 2; COMB LOOP Node = 'ram~7156'" { { "Info" "ITDB_PART_OF_SCC" "ram\[2\]\[6\]~7157 LCCOMB_X14_Y6_N4 " "Info: Loc. = LCCOMB_X14_Y6_N4; Node \"ram\[2\]\[6\]~7157\"" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { ram[2][6]~7157 } "NODE_NAME" } } } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0} { "Info" "ITDB_PART_OF_SCC" "ram~7156 LCCOMB_X13_Y9_N2 " "Info: Loc. = LCCOMB_X13_Y9_N2; Node \"ram~7156\"" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { ram~7156 } "NODE_NAME" } } } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0} } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { ram[2][6]~7157 } "NODE_NAME" } } { "shop.vhd" "" { Text "D:/my_eda2/shop/shop.vhd" 52 -1 0 } } { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { ram~7156 } "NODE_NAME" } } { "shop.vhd" "" { Text "D:/my_eda2/shop/shop.vhd" 21 -1 0 } } { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "9.848 ns" { set ram~7156 } "NODE_NAME" } } { "shop.vhd" "" { Text "D:/my_eda2/shop/shop.vhd" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.090 ns) + CELL(0.206 ns) 12.088 ns ram\[2\]\[6\]~1933 3 REG LCCOMB_X14_Y6_N0 4 " "Info: 3: + IC(1.090 ns) + CELL(0.206 ns) = 12.088 ns; Loc. = LCCOMB_X14_Y6_N0; Fanout = 4; REG Node = 'ram\[2\]\[6\]~1933'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.296 ns" { ram~7156 ram[2][6]~1933 } "NODE_NAME" } } { "shop.vhd" "" { Text "D:/my_eda2/shop/shop.vhd" 52 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.998 ns ( 90.98 % ) " "Info: Total cell delay = 10.998 ns ( 90.98 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.090 ns ( 9.02 % ) " "Info: Total interconnect delay = 1.090 ns ( 9.02 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "12.088 ns" { set ram~7156 ram[2][6]~1933 } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "12.088 ns" { set set~combout ram~7156 ram[2][6]~1933 } { 0.000ns 0.000ns 0.000ns 1.090ns } { 0.000ns 0.944ns 9.848ns 0.206ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.369 ns + " "Info: + Micro setup delay of destination is 1.369 ns" { } { { "shop.vhd" "" { Text "D:/my_eda2/shop/shop.vhd" 52 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "set destination 3.528 ns - Shortest register " "Info: - Shortest clock path from clock \"set\" to destination register is 3.528 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.944 ns) 0.944 ns set 1 CLK PIN_133 172 " "Info: 1: + IC(0.000 ns) + CELL(0.944 ns) = 0.944 ns; Loc. = PIN_133; Fanout = 172; CLK Node = 'set'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { set } "NODE_NAME" } } { "shop.vhd" "" { Text "D:/my_eda2/shop/shop.vhd" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.218 ns) + CELL(0.366 ns) 3.528 ns ram\[2\]\[6\]~1933 2 REG LCCOMB_X14_Y6_N0 4 " "Info: 2: + IC(2.218 ns) + CELL(0.366 ns) = 3.528 ns; Loc. = LCCOMB_X14_Y6_N0; Fanout = 4; REG Node = 'ram\[2\]\[6⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -