shop.map.qmsg

大量VHDL写的数字系统设计有用实例达到

{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "cnt data_in GND " "Warning: Reduced register \"cnt\" with stuck data_in port to stuck value GND" {  } { { "shop.vhd" "" { Text "D:/my_eda2/shop/shop.vhd" 41 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "clk1hz \\process8:cnt\[0\] " "Info: Duplicate register \"clk1hz\" merged to single register \"\\process8:cnt\[0\]\"" {  } { { "shop.vhd" "" { Text "D:/my_eda2/shop/shop.vhd" 22 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Info" "IOPT_MLS_CREATED_ALOAD_CCT" "" "Info: Converted presettable and clearable register to equivalent circuits with latches. Registers will power-up to an undefined state, and DEVCLRn will place the registers in an undefined state." { { "Info" "IOPT_MLS_CREATED_ALOAD_CCT_SUB" "ram\[2\]\[0\] ram\[2\]\[0\]~_emulated ram\[2\]\[0\]~1669 " "Info: Register \"ram\[2\]\[0\]\" converted into equivalent circuit using register \"ram\[2\]\[0\]~_emulated\" and latch \"ram\[2\]\[0\]~1669\"" {  } { { "shop.vhd" "" { Text "D:/my_eda2/shop/shop.vhd" 52 -1 0 } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0} { "Info" "IOPT_MLS_CREATED_ALOAD_CCT_SUB" "ram\[1\]\[0\] ram\[1\]\[0\]~_emulated ram\[1\]\[0\]~1680 " "Info: Register \"ram\[1\]\[0\]\" converted into equivalent circuit using register \"ram\[1\]\[0\]~_emulated\" and latch \"ram\[1\]\[0\]~1680\"" {  } { { "shop.vhd" "" { Text "D:/my_eda2/shop/shop.vhd" 52 -1 0 } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0} { "Info" "IOPT_MLS_CREATED_ALOAD_CCT_SUB" "ram\[0\]\[0\] ram\[0\]\[0\]~_emulated ram\[0\]\[0\]~1691 " "Info: Register \"ram\[0\]\[0\]\" converted into equivalent circuit using register \"ram\[0\]\[0\]~_emulated\" and latch \"ram\[0\]\[0\]~1691\"" {  } { { "shop.vhd" "" { Text "D:/my_eda2/shop/shop.vhd" 52 -1 0 } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0} { "Info" "IOPT_MLS_CREATED_ALOAD_CCT_SUB" "ram\[3\]\[0\] ram\[3\]\[0\]~_emulated ram\[3\]\[0\]~1702 " "Info: Register \"ram\[3\]\[0\]\" converted into equivalent circuit using register \"ram\[3\]\[0\]~_emulated\" and latch \"ram\[3\]\[0\]~1702\"" {  } { { "shop.vhd" "" { Text "D:/my_eda2/shop/shop.vhd" 52 -1 0 } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0} { "Info" "IOPT_MLS_CREATED_ALOAD_CCT_SUB" "ram\[1\]\[1\] ram\[1\]\[1\]~_emulated ram\[1\]\[1\]~1713 " "Info: Register \"ram\[1\]\[1\]\" converted into equivalent circuit using register \"ram\[1\]\[1\]~_emulated\" and latch \"ram\[1\]\[1\]~1713\"" {  } { { "shop.vhd" "" { Text "D:/my_eda2/shop/shop.vhd" 52 -1 0 } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0} { "Info" "IOPT_MLS_CREATED_ALOAD_CCT_SUB" "ram\[2\]\[1\] ram\[2\]\[1\]~_emulated ram\[2\]\[1\]~1724 " "Info: Register \"ram\[2\]\[1\]\" converted into equivalent circuit using register \"ram\[2\]\[1\]~_emulated\" and latch \"ram\[2\]\[1\]~1724\"" {  } { { "shop.vhd" "" { Text "D:/my_eda2/shop/shop.vhd" 52 -1 0 } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0} { "Info" "IOPT_MLS_CREATED_ALOAD_CCT_SUB" "ram\[0\]\[1\] ram\[0\]\[1\]~_emulated ram\[0\]\[1\]~1735 " "Info: Register \"ram\[0\]\[1\]\" converted into equivalent circuit using register \"ram\[0\]\[1\]~_emulated\" and latch \"ram\[0\]\[1\]~1735\"" {  } { { "shop.vhd" "" { Text "D:/my_eda2/shop/shop.vhd" 52 -1 0 } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0} { "Info" "IOPT_MLS_CREATED_ALOAD_CCT_SUB" "ram\[3\]\[1\] ram\[3\]\[1\]~_emulated ram\[3\]\[1\]~1746 " "Info: Register \"ram\[3\]\[1\]\" converted into equivalent circuit using register \"ram\[3\]\[1\]~_emulated\" and latch \"ram\[3\]\[1\]~1746\"" {  } { { "shop.vhd" "" { Text "D:/my_eda2/shop/shop.vhd" 52 -1 0 } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0} { "Info" "IOPT_MLS_CREATED_ALOAD_CCT_SUB" "ram\[2\]\[2\] ram\[2\]\[2\]~_emulated ram\[2\]\[2\]~1757 " "Info: Register \"ram\[2\]\[2\]\" converted into equivalent circuit using register \"ram\[2\]\[2\]~_emulated\" and latch \"ram\[2\]\[2\]~1757\"" {  } { { "shop.vhd" "" { Text "D:/my_eda2/shop/shop.vhd" 52 -1 0 } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0} { "Info" "IOPT_MLS_CREATED_ALOAD_CCT_SUB" "ram\[1\]\[2\] ram\[1\]\[2\]~_emulated ram\[1\]\[2\]~1768 " "Info: Register \"ram\[1\]\[2\]\" converted into equivalent circuit using register \"ram\[1\]\[2\]~_emulated\" and latch \"ram\[1\]\[2\]~1768\"" {  } { { "shop.vhd" "" { Text "D:/my_eda2/shop/shop.vhd" 52 -1 0 } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0} { "Info" "IOPT_MLS_CREATED_ALOAD_CCT_SUB" "ram\[0\]\[2\] ram\[0\]\[2\]~_emulated ram\[0\]\[2\]~1779 " "Info: Register \"ram\[0\]\[2\]\" converted into equivalent circuit using register \"ram\[0\]\[2\]~_emulated\" and latch \"ram\[0\]\[2\]~1779\"" {  } { { "shop.vhd" "" { Text "D:/my_eda2/shop/shop.vhd" 52 -1 0 } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0} { "Info" "IOPT_MLS_CREATED_ALOAD_CCT_SUB" "ram\[3\]\[2\] ram\[3\]\[2\]~_emulated ram\[3\]\[2\]~1790 " "Info: Register \"ram\[3\]\[2\]\" converted into equivalent circuit using register \"ram\[3\]\[2\]~_emulated\" and latch \"ram\[3\]\[2\]~1790\"" {  } { { "shop.vhd" "" { Text "D:/my_eda2/shop/shop.vhd" 52 -1 0 } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0} { "Info" "IOPT_MLS_CREATED_ALOAD_CCT_SUB" "ram\[1\]\[3\] ram\[1\]\[3\]~_emulated ram\[1\]\[3\]~1801 " "Info: Register \"ram\[1\]\[3\]\" converted into equivalent circuit using register \"ram\[1\]\[3\]~_emulated\" and latch \"ram\[1\]\[3\]~1801\"" {  } { { "shop.vhd" "" { Text "D:/my_eda2/shop/shop.vhd" 52 -1 0 } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0} { "Info" "IOPT_MLS_CREATED_ALOAD_CCT_SUB" "ram\[2\]\[3\] ram\[2\]\[3\]~_emulated ram\[2\]\[3\]~1812 " "Info: Register \"ram\[2\]\[3\]\" converted into equivalent circuit using register \"ram\[2\]\[3\]~_emulated\" and latch \"ram\[2\]\[3\]~1812\"" {  } { { "shop.vhd" "" { Text "D:/my_eda2/shop/shop.vhd" 52 -1 0 } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0} { "Info" "IOPT_MLS_CREATED_ALOAD_CCT_SUB" "ram\[0\]\[3\] ram\[0\]\[3\]~_emulated ram\[0\]\[3\]~1823 " "Info: Register \"ram\[0\]\[3\]\" converted into equivalent circuit using register \"ram\[0\]\[3\]~_emulated\" and latch \"ram\[0\]\[3\]~1823\"" {  } { { "shop.vhd" "" { Text "D:/my_eda2/shop/shop.vhd" 52 -1 0 } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0} { "Info" "IOPT_MLS_CREATED_ALOAD_CCT_SUB" "ram\[3\]\[3\] ram\[3\]\[3\]~_emulated ram\[3\]\[3\]~1834 " "Info: Register \"ram\[3\]\[3\]\" converted into equivalent circuit using register \"ram\[3\]\[3\]~_emulated\" and latch \"ram\[3\]\[3\]~1834\"" {  } { { "shop.vhd" "" { Text "D:/my_eda2/shop/shop.vhd" 52 -1 0 } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0} { "Info" "IOPT_MLS_CREATED_ALOAD_CCT_SUB" "ram\[2\]\[4\] ram\[2\]\[4\]~_emulated ram\[2\]\[4\]~1845 " "Info: Register \"ram\[2\]\[4\]\" converted into equivalent circuit using register \"ram\[2\]\[4\]~_emulated\" and latch \"ram\[2\]\[4\]~1845\"" {  } { { "shop.vhd" "" { Text "D:/my_eda2/shop/shop.vhd" 52 -1 0 } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0} { "Info" "IOPT_MLS_CREATED_ALOAD_CCT_SUB" "ram\[1\]\[4\] ram\[1\]\[4\]~_emulated ram\[1\]\[4\]~1856 " "Info: Register \"ram\[1\]\[4\]\" converted into equivalent circuit using register \"ram\[1\]\[4\]~_emulated\" and latch \"ram\[1\]\[4\]~1856\"" {  } { { "shop.vhd" "" { Text "D:/my_eda2/shop/shop.vhd" 52 -1 0 } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0} { "Info" "IOPT_MLS_CREATED_ALOAD_CCT_SUB" "ram\[0\]\[4\] ram\[0\]\[4\]~_emulated ram\[0\]\[4\]~1867 " "Info: Register \"ram\[0\]\[4\]\" converted into equivalent circuit using register \"ram\[0\]\[4\]~_emulated\" and latch \"ram\[0\]\[4\]~1867\"" {  } { { "shop.vhd" "" { Text "D:/my_eda2/shop/shop.vhd" 52 -1 0 } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0} { "Info" "IOPT_MLS_CREATED_ALOAD_CCT_SUB" "ram\[3\]\[4\] ram\[3\]\[4\]~_emulated ram\[3\]\[4\]~1878 " "Info: Register \"ram\[3\]\[4\]\" converted into equivalent circuit using register \"ram\[3\]\[4\]~_emulated\" and latch \"ram\[3\]\[4\]~1878\"" {  } { { "shop.vhd" "" { Text "D:/my_eda2/shop/shop.vhd" 52 -1 0 } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0} { "Info" "IOPT_MLS_CREATED_ALOAD_CCT_SUB" "ram\[1\]\[5\] ram\[1\]\[5\]~_emulated ram\[1\]\[5\]~1889 " "Info: Register \"ram\[1\]\[5\]\" converted into equivalent circuit using register \"ram\[1\]\[5\]~_emulated\" and latch \"ram\[1\]\[5\]~1889\"" {  } { { "shop.vhd" "" { Text "D:/my_eda2/shop/shop.vhd" 52 -1 0 } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0} { "Info" "IOPT_MLS_CREATED_ALOAD_CCT_SUB" "ram\[2\]\[5\] ram\[2\]\[5\]~_emulated ram\[2\]\[5\]~1900 " "Info: Register \"ram\[2\]\[5\]\" converted into equivalent circuit using register \"ram\[2\]\[5\]~_emulated\" and latch \"ram\[2\]\[5\]~1900\"" {  } { { "shop.vhd" "" { Text "D:/my_eda2/shop/shop.vhd" 52 -1 0 } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0} { "Info" "IOPT_MLS_CREATED_ALOAD_CCT_SUB" "ram\[0\]\[5\] ram\[0\]\[5\]~_emulated ram\[0\]\[5\]~1911 " "Info: Register \"ram\[0\]\[5\]\" converted into equivalent circuit using register \"ram\[0\]\[5\]~_emulated\" and latch \"ram\[0\]\[5\]~1911\"" {  } { { "shop.vhd" "" { Text "D:/my_eda2/shop/shop.vhd" 52 -1 0 } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0} { "Info" "IOPT_MLS_CREATED_ALOAD_CCT_SUB" "ram\[3\]\[5\] ram\[3\]\[5\]~_emulated ram\[3\]\[5\]~1922 " "Info: Register \"ram\[3\]\[5\]\" converted into equivalent circuit using register \"ram\[3\]\[5\]~_emulated\" and latch \"ram\[3\]\[5\]~1922\"" {  } { { "shop.vhd" "" { Text "D:/my_eda2/shop/shop.vhd" 52 -1 0 } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0} { "Info" "IOPT_MLS_CREATED_ALOAD_CCT_SUB" "ram\[2\]\[6\] ram\[2\]\[6\]~_emulated ram\[2\]\[6\]~1933 " "Info: Register \"ram\[2\]\[6\]\" converted into equivalent circuit using register \"ram\[2\]\[6\]~_emulated\" and latch \"ram\[2\]\[6\]~1933\"" {  } { { "shop.vhd" "" { Text "D:/my_eda2/shop/shop.vhd" 52 -1 0 } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0} { "Info" "IOPT_MLS_CREATED_ALOAD_CCT_SUB" "ram\[1\]\[6\] ram\[1\]\[6\]~_emulated ram\[1\]\[6\]~1944 " "Info: Register \"ram\[1\]\[6\]\" converted into equivalent circuit using register \"ram\[1\]\[6\]~_emulated\" and latch \"ram\[1\]\[6\]~1944\"" {  } { { "shop.vhd" "" { Text "D:/my_eda2/shop/shop.vhd" 52 -1 0 } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0} { "Info" "IOPT_MLS_CREATED_ALOAD_CCT_SUB" "ram\[0\]\[6\] ram\[0\]\[6\]~_emulated ram\[0\]\[6\]~1955 " "Info: Register \"ram\[0\]\[6\]\" converted into equivalent circuit using register \"ram\[0\]\[6\]~_emulated\" and latch \"ram\[0\]\[6\]~1955\"" {  } { { "shop.vhd" "" { Text "D:/my_eda2/shop/shop.vhd" 52 -1 0 } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0} { "Info" "IOPT_MLS_CREATED_ALOAD_CCT_SUB" "ram\[3\]\[6\] ram\[3\]\[6\]~_emulated ram\[3\]\[6\]~1966 " "Info: Register \"ram\[3\]\[6\]\" converted into equivalent circuit using register \"ram\[3\]\[6\]~_emulated\" and latch \"ram\[3\]\[6\]~1966\"" {  } { { "shop.vhd" "" { Text "D:/my_eda2/shop/shop.vhd" 52 -1 0 } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0} { "Info" "IOPT_MLS_CREATED_ALOAD_CCT_SUB" "ram\[1\]\[7\] ram\[1\]\[7\]~_emulated ram\[1\]\[7\]~1977 " "Info: Register \"ram\[1\]\[7\]\" converted into equivalent circuit using register \"ram\[1\]\[7\]~_emulated\" and latch \"ram\[1\]\[7\]~1977\"" {  } { { "shop.vhd" "" { Text "D:/my_eda2/shop/shop.vhd" 52 -1 0 } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0} { "Info" "IOPT_MLS_CREATED_ALOAD_CCT_SUB" "ram\[2\]\[7\] ram\[2\]\[7\]~_emulated ram\[2\]\[7\]~1988 " "Info: Register \"ram\[2\]\[7\]\" converted into equivalent circuit using register \"ram\[2\]\[7\]~_emulated\" and latch \"ram\[2\]\[7\]~1988\"" {  } { { "shop.vhd" "" { Text "D:/my_eda2/shop/shop.vhd" 52 -1 0 } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0} { "Info" "IOPT_MLS_CREATED_ALOAD_CCT_SUB" "ram\[0\]\[7\] ram\[0\]\[7\]~_emulated ram\[0\]\[7\]~1999 " "Info: Register \"ram\[0\]\[7\]\" converted into equivalent circuit using register \"ram\[0\]\[7\]~_emulated\" and latch \"ram\[0\]\[7\]~1999\"" {  } { { "shop.vhd" "" { Text "D:/my_eda2/shop/shop.vhd" 52 -1 0 } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0} { "Info" "IOPT_MLS_CREATED_ALOAD_CCT_SUB" "ram\[3\]\[7\] ram\[3\]\[7\]~_emulated ram\[3\]\[7\]~2010 " "Info: Register \"ram\[3\]\[7\]\" converted into equivalent circuit using register \"ram\[3\]\[7\]~_emulated\" and latch \"ram\[3\]\[7\]~2010\"" {  } { { "shop.vhd" "" { Text "D:/my_eda2/shop/shop.vhd" 52 -1 0 } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0}  } {  } 0 0 "Converted presettable and clearable register to equivalent circuits with latches. Registers will power-up to an undefined state, and DEVCLRn will place the registers in an undefined state." 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "295 " "Info: Implemented 295 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "15 " "Info: Implemented 15 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "20 " "Info: Implemented 20 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "260 " "Info: Implemented 260 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 2 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "141 " "Info: Allocated 141 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon Apr 16 15:57:01 2007 " "Info: Processing ended: Mon Apr 16 15:57:01 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Info: Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}