shop.fit.smsg

大量VHDL写的数字系统设计有用实例达到

Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Mon Apr 16 15:57:08 2007
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off shop -c shop
Info: Selected device EP2C8T144C8 for design "shop"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Fitter is using the Classic Timing Analyzer
Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time.
Info: The Fitter has identified 1 logical partitions of which 0 have a previous placement to use
    Info: Previous placement does not exist for 341 of 341 atoms in partition Top
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EP2C5T144C8 is compatible
    Info: Device EP2C5T144I8 is compatible
    Info: Device EP2C8T144I8 is compatible
Info: Fitter converted 3 user pins into dedicated programming pins
    Info: Pin ~ASDO~ is reserved at location 1
    Info: Pin ~nCSO~ is reserved at location 2
    Info: Pin ~LVDS54p/nCEO~ is reserved at location 76
Info: Automatically promoted node \process8:cnt[0] 
    Info: Automatically promoted destinations to use location or clock signal Global Clock
    Info: Following destination nodes may be non-global or may not use global or regional clocks
        Info: Destination node Mux40~127
        Info: Destination node Mux39~128
        Info: Destination node Mux38~128
        Info: Destination node Mux37~128
        Info: Destination node Mux36~128
        Info: Destination node Mux35~128
        Info: Destination node Mux34~128
        Info: Destination node Mux33~6
        Info: Destination node \process8:cnt[1]~11
        Info: Destination node \process8:cnt[0]~9
        Info: Non-global destination nodes limited to 10 nodes
Info: Automatically promoted node clk1khz 
    Info: Automatically promoted destinations to use location or clock signal Global Clock
    Info: Following destination nodes may be non-global or may not use global or regional clocks
        Info: Destination node clk1khz~2
Info: Starting register packing
Info: Finished register packing: elapsed time is 00:00:00
    Extra Info: No registers were packed into other blocks
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Estimated most critical path is register to register delay of 7.304 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X13_Y9; Fanout = 120; REG Node = 'item[0]'
    Info: 2: + IC(0.000 ns) + CELL(2.621 ns) = 2.621 ns; Loc. = LAB_X14_Y9; Fanout = 2; COMB LOOP Node = 'ram[1][2]~7127'
        Info: Loc. = LAB_X14_Y9; Node "ram[1][2]~7127"
        Info: Loc. = LAB_X14_Y9; Node "ram~7126"
    Info: 3: + IC(0.902 ns) + CELL(0.624 ns) = 4.147 ns; Loc. = LAB_X14_Y8; Fanout = 1; COMB Node = 'qua~210'
    Info: 4: + IC(1.167 ns) + CELL(0.366 ns) = 5.680 ns; Loc. = LAB_X14_Y6; Fanout = 1; COMB Node = 'qua~211'
    Info: 5: + IC(0.865 ns) + CELL(0.651 ns) = 7.196 ns; Loc. = LAB_X18_Y6; Fanout = 1; COMB Node = 'qua[2]~143'
    Info: 6: + IC(0.000 ns) + CELL(0.108 ns) = 7.304 ns; Loc. = LAB_X18_Y6; Fanout = 15; REG Node = 'qua[2]'
    Info: Total cell delay = 4.370 ns ( 59.83 % )
    Info: Total interconnect delay = 2.934 ns ( 40.17 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 1% of the available device resources. Peak interconnect usage is 3%
    Info: The peak interconnect region extends from location X11_Y0 to location X22_Y9
Info: Fitter routing operations ending: elapsed time is 00:00:01
Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
    Info: Optimizations that may affect the design's routability were skipped
    Info: Optimizations that may affect the design's timing were skipped
Info: Started post-fitting delay annotation
Warning: Found 20 output pins without output pin load capacitance assignment
    Info: Pin "item0[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "item0[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "item0[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "item0[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "act[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "act[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "act[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "act[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "seg7[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "seg7[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "seg7[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "seg7[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "seg7[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "seg7[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "seg7[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "scan[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "scan[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "scan[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "act10" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "act5" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Delay annotation completed successfully
Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Info: Quartus II Fitter was successful. 0 errors, 2 warnings
    Info: Allocated 175 megabytes of memory during processing
    Info: Processing ended: Mon Apr 16 15:57:18 2007
    Info: Elapsed time: 00:00:10