lpm_fifo.hier_info

大量VHDL写的数字系统设计有用实例达到

|lpm_fifo
full <= fifo:inst.full
wrreq => fifo:inst.wrreq
rdreq => fifo:inst.rdreq
clock => fifo:inst.clock
data[0] => fifo:inst.data[0]
data[1] => fifo:inst.data[1]
data[2] => fifo:inst.data[2]
data[3] => fifo:inst.data[3]
data[4] => fifo:inst.data[4]
data[5] => fifo:inst.data[5]
data[6] => fifo:inst.data[6]
data[7] => fifo:inst.data[7]
empty <= fifo:inst.empty
q[0] <= fifo:inst.q[0]
q[1] <= fifo:inst.q[1]
q[2] <= fifo:inst.q[2]
q[3] <= fifo:inst.q[3]
q[4] <= fifo:inst.q[4]
q[5] <= fifo:inst.q[5]
q[6] <= fifo:inst.q[6]
q[7] <= fifo:inst.q[7]
usedw[0] <= fifo:inst.usedw[0]
usedw[1] <= fifo:inst.usedw[1]
usedw[2] <= fifo:inst.usedw[2]
usedw[3] <= fifo:inst.usedw[3]
usedw[4] <= fifo:inst.usedw[4]


|lpm_fifo|fifo:inst
clock => scfifo:scfifo_component.clock
data[0] => scfifo:scfifo_component.data[0]
data[1] => scfifo:scfifo_component.data[1]
data[2] => scfifo:scfifo_component.data[2]
data[3] => scfifo:scfifo_component.data[3]
data[4] => scfifo:scfifo_component.data[4]
data[5] => scfifo:scfifo_component.data[5]
data[6] => scfifo:scfifo_component.data[6]
data[7] => scfifo:scfifo_component.data[7]
rdreq => scfifo:scfifo_component.rdreq
wrreq => scfifo:scfifo_component.wrreq
empty <= scfifo:scfifo_component.empty
full <= scfifo:scfifo_component.full
q[0] <= scfifo:scfifo_component.q[0]
q[1] <= scfifo:scfifo_component.q[1]
q[2] <= scfifo:scfifo_component.q[2]
q[3] <= scfifo:scfifo_component.q[3]
q[4] <= scfifo:scfifo_component.q[4]
q[5] <= scfifo:scfifo_component.q[5]
q[6] <= scfifo:scfifo_component.q[6]
q[7] <= scfifo:scfifo_component.q[7]
usedw[0] <= scfifo:scfifo_component.usedw[0]
usedw[1] <= scfifo:scfifo_component.usedw[1]
usedw[2] <= scfifo:scfifo_component.usedw[2]
usedw[3] <= scfifo:scfifo_component.usedw[3]
usedw[4] <= scfifo:scfifo_component.usedw[4]


|lpm_fifo|fifo:inst|scfifo:scfifo_component
data[0] => scfifo_0mv:auto_generated.data[0]
data[1] => scfifo_0mv:auto_generated.data[1]
data[2] => scfifo_0mv:auto_generated.data[2]
data[3] => scfifo_0mv:auto_generated.data[3]
data[4] => scfifo_0mv:auto_generated.data[4]
data[5] => scfifo_0mv:auto_generated.data[5]
data[6] => scfifo_0mv:auto_generated.data[6]
data[7] => scfifo_0mv:auto_generated.data[7]
q[0] <= scfifo_0mv:auto_generated.q[0]
q[1] <= scfifo_0mv:auto_generated.q[1]
q[2] <= scfifo_0mv:auto_generated.q[2]
q[3] <= scfifo_0mv:auto_generated.q[3]
q[4] <= scfifo_0mv:auto_generated.q[4]
q[5] <= scfifo_0mv:auto_generated.q[5]
q[6] <= scfifo_0mv:auto_generated.q[6]
q[7] <= scfifo_0mv:auto_generated.q[7]
wrreq => scfifo_0mv:auto_generated.wrreq
rdreq => scfifo_0mv:auto_generated.rdreq
clock => scfifo_0mv:auto_generated.clock
aclr => ~NO_FANOUT~
sclr => ~NO_FANOUT~
empty <= scfifo_0mv:auto_generated.empty
full <= scfifo_0mv:auto_generated.full
almost_full <= <GND>
almost_empty <= <GND>
usedw[0] <= scfifo_0mv:auto_generated.usedw[0]
usedw[1] <= scfifo_0mv:auto_generated.usedw[1]
usedw[2] <= scfifo_0mv:auto_generated.usedw[2]
usedw[3] <= scfifo_0mv:auto_generated.usedw[3]
usedw[4] <= scfifo_0mv:auto_generated.usedw[4]


|lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated
clock => a_dpfifo_7sv:dpfifo.clock
data[0] => a_dpfifo_7sv:dpfifo.data[0]
data[1] => a_dpfifo_7sv:dpfifo.data[1]
data[2] => a_dpfifo_7sv:dpfifo.data[2]
data[3] => a_dpfifo_7sv:dpfifo.data[3]
data[4] => a_dpfifo_7sv:dpfifo.data[4]
data[5] => a_dpfifo_7sv:dpfifo.data[5]
data[6] => a_dpfifo_7sv:dpfifo.data[6]
data[7] => a_dpfifo_7sv:dpfifo.data[7]
empty <= a_dpfifo_7sv:dpfifo.empty
full <= a_dpfifo_7sv:dpfifo.full
q[0] <= a_dpfifo_7sv:dpfifo.q[0]
q[1] <= a_dpfifo_7sv:dpfifo.q[1]
q[2] <= a_dpfifo_7sv:dpfifo.q[2]
q[3] <= a_dpfifo_7sv:dpfifo.q[3]
q[4] <= a_dpfifo_7sv:dpfifo.q[4]
q[5] <= a_dpfifo_7sv:dpfifo.q[5]
q[6] <= a_dpfifo_7sv:dpfifo.q[6]
q[7] <= a_dpfifo_7sv:dpfifo.q[7]
rdreq => a_dpfifo_7sv:dpfifo.rreq
usedw[0] <= a_dpfifo_7sv:dpfifo.usedw[0]
usedw[1] <= a_dpfifo_7sv:dpfifo.usedw[1]
usedw[2] <= a_dpfifo_7sv:dpfifo.usedw[2]
usedw[3] <= a_dpfifo_7sv:dpfifo.usedw[3]
usedw[4] <= a_dpfifo_7sv:dpfifo.usedw[4]
wrreq => a_dpfifo_7sv:dpfifo.wreq


|lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo
clock => altsyncram_qla1:FIFOram.clock0
clock => altsyncram_qla1:FIFOram.clock1
clock => cntr_rua:rd_ptr_msb.clock
clock => cntr_8v6:usedw_counter.clock
clock => cntr_sua:wr_ptr.clock
clock => empty_dff.CLK
clock => full_dff.CLK
clock => low_addressa[4].CLK
clock => low_addressa[3].CLK
clock => low_addressa[2].CLK
clock => low_addressa[1].CLK
clock => low_addressa[0].CLK
clock => rd_ptr_lsb.CLK
clock => usedw_is_0_dff.CLK
clock => usedw_is_1_dff.CLK
clock => wrreq_delay.CLK
data[0] => altsyncram_qla1:FIFOram.data_a[0]
data[1] => altsyncram_qla1:FIFOram.data_a[1]
data[2] => altsyncram_qla1:FIFOram.data_a[2]
data[3] => altsyncram_qla1:FIFOram.data_a[3]
data[4] => altsyncram_qla1:FIFOram.data_a[4]
data[5] => altsyncram_qla1:FIFOram.data_a[5]
data[6] => altsyncram_qla1:FIFOram.data_a[6]
data[7] => altsyncram_qla1:FIFOram.data_a[7]
empty <= empty_out.DB_MAX_OUTPUT_PORT_TYPE
full <= full_dff.DB_MAX_OUTPUT_PORT_TYPE
q[0] <= altsyncram_qla1:FIFOram.q_b[0]
q[1] <= altsyncram_qla1:FIFOram.q_b[1]
q[2] <= altsyncram_qla1:FIFOram.q_b[2]
q[3] <= altsyncram_qla1:FIFOram.q_b[3]
q[4] <= altsyncram_qla1:FIFOram.q_b[4]
q[5] <= altsyncram_qla1:FIFOram.q_b[5]
q[6] <= altsyncram_qla1:FIFOram.q_b[6]
q[7] <= altsyncram_qla1:FIFOram.q_b[7]
rreq => valid_rreq.IN0
sclr => cntr_rua:rd_ptr_msb.sclr
sclr => cntr_8v6:usedw_counter.sclr
sclr => cntr_sua:wr_ptr.sclr
usedw[0] <= cntr_8v6:usedw_counter.q[0]
usedw[1] <= cntr_8v6:usedw_counter.q[1]
usedw[2] <= cntr_8v6:usedw_counter.q[2]
usedw[3] <= cntr_8v6:usedw_counter.q[3]
usedw[4] <= cntr_8v6:usedw_counter.q[4]
wreq => valid_wreq.IN0


|lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|altsyncram_qla1:FIFOram
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[3] => ram_block1a4.PORTAADDR3
address_a[3] => ram_block1a5.PORTAADDR3
address_a[3] => ram_block1a6.PORTAADDR3
address_a[3] => ram_block1a7.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[4] => ram_block1a2.PORTAADDR4
address_a[4] => ram_block1a3.PORTAADDR4
address_a[4] => ram_block1a4.PORTAADDR4
address_a[4] => ram_block1a5.PORTAADDR4
address_a[4] => ram_block1a6.PORTAADDR4
address_a[4] => ram_block1a7.PORTAADDR4
address_b[0] => ram_block1a0.PORTBADDR
address_b[0] => ram_block1a1.PORTBADDR
address_b[0] => ram_block1a2.PORTBADDR
address_b[0] => ram_block1a3.PORTBADDR
address_b[0] => ram_block1a4.PORTBADDR
address_b[0] => ram_block1a5.PORTBADDR
address_b[0] => ram_block1a6.PORTBADDR
address_b[0] => ram_block1a7.PORTBADDR
address_b[1] => ram_block1a0.PORTBADDR1
address_b[1] => ram_block1a1.PORTBADDR1
address_b[1] => ram_block1a2.PORTBADDR1
address_b[1] => ram_block1a3.PORTBADDR1
address_b[1] => ram_block1a4.PORTBADDR1
address_b[1] => ram_block1a5.PORTBADDR1
address_b[1] => ram_block1a6.PORTBADDR1
address_b[1] => ram_block1a7.PORTBADDR1
address_b[2] => ram_block1a0.PORTBADDR2
address_b[2] => ram_block1a1.PORTBADDR2
address_b[2] => ram_block1a2.PORTBADDR2
address_b[2] => ram_block1a3.PORTBADDR2
address_b[2] => ram_block1a4.PORTBADDR2
address_b[2] => ram_block1a5.PORTBADDR2
address_b[2] => ram_block1a6.PORTBADDR2
address_b[2] => ram_block1a7.PORTBADDR2
address_b[3] => ram_block1a0.PORTBADDR3
address_b[3] => ram_block1a1.PORTBADDR3
address_b[3] => ram_block1a2.PORTBADDR3
address_b[3] => ram_block1a3.PORTBADDR3
address_b[3] => ram_block1a4.PORTBADDR3
address_b[3] => ram_block1a5.PORTBADDR3
address_b[3] => ram_block1a6.PORTBADDR3
address_b[3] => ram_block1a7.PORTBADDR3
address_b[4] => ram_block1a0.PORTBADDR4
address_b[4] => ram_block1a1.PORTBADDR4
address_b[4] => ram_block1a2.PORTBADDR4
address_b[4] => ram_block1a3.PORTBADDR4
address_b[4] => ram_block1a4.PORTBADDR4
address_b[4] => ram_block1a5.PORTBADDR4
address_b[4] => ram_block1a6.PORTBADDR4
address_b[4] => ram_block1a7.PORTBADDR4
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0
clock0 => ram_block1a4.CLK0
clock0 => ram_block1a5.CLK0
clock0 => ram_block1a6.CLK0
clock0 => ram_block1a7.CLK0
clock1 => ram_block1a0.CLK1
clock1 => ram_block1a1.CLK1
clock1 => ram_block1a2.CLK1
clock1 => ram_block1a3.CLK1
clock1 => ram_block1a4.CLK1
clock1 => ram_block1a5.CLK1
clock1 => ram_block1a6.CLK1
clock1 => ram_block1a7.CLK1
clocken1 => ram_block1a0.ENA1
clocken1 => ram_block1a1.ENA1
clocken1 => ram_block1a2.ENA1
clocken1 => ram_block1a3.ENA1
clocken1 => ram_block1a4.ENA1
clocken1 => ram_block1a5.ENA1
clocken1 => ram_block1a6.ENA1
clocken1 => ram_block1a7.ENA1
data_a[0] => ram_block1a0.PORTADATAIN
data_a[1] => ram_block1a1.PORTADATAIN
data_a[2] => ram_block1a2.PORTADATAIN
data_a[3] => ram_block1a3.PORTADATAIN
data_a[4] => ram_block1a4.PORTADATAIN
data_a[5] => ram_block1a5.PORTADATAIN
data_a[6] => ram_block1a6.PORTADATAIN
data_a[7] => ram_block1a7.PORTADATAIN
q_b[0] <= ram_block1a0.PORTBDATAOUT
q_b[1] <= ram_block1a1.PORTBDATAOUT
q_b[2] <= ram_block1a2.PORTBDATAOUT
q_b[3] <= ram_block1a3.PORTBDATAOUT
q_b[4] <= ram_block1a4.PORTBDATAOUT
q_b[5] <= ram_block1a5.PORTBDATAOUT
q_b[6] <= ram_block1a6.PORTBDATAOUT
q_b[7] <= ram_block1a7.PORTBDATAOUT
wren_a => ram_block1a0.PORTAWE
wren_a => ram_block1a1.PORTAWE
wren_a => ram_block1a2.PORTAWE
wren_a => ram_block1a3.PORTAWE
wren_a => ram_block1a4.PORTAWE
wren_a => ram_block1a5.PORTAWE
wren_a => ram_block1a6.PORTAWE
wren_a => ram_block1a7.PORTAWE


|lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|cntr_rua:rd_ptr_msb
clock => counter_cella0.CLK
clock => counter_cella1.CLK
clock => counter_cella2.CLK
clock => counter_cella3.CLK
cnt_en => counter_cella0.DATAB
cnt_en => counter_cella1.DATAB
cnt_en => counter_cella2.DATAB
cnt_en => counter_cella3.DATAB
q[0] <= counter_cella0.REGOUT
q[1] <= counter_cella1.REGOUT
q[2] <= counter_cella2.REGOUT
q[3] <= counter_cella3.REGOUT
sclr => counter_cella0.SCLR
sclr => counter_cella1.SCLR
sclr => counter_cella2.SCLR
sclr => counter_cella3.SCLR


|lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|cntr_8v6:usedw_counter
clock => counter_cella0.CLK
clock => counter_cella1.CLK
clock => counter_cella2.CLK
clock => counter_cella3.CLK
clock => counter_cella4.CLK
q[0] <= counter_cella0.REGOUT
q[1] <= counter_cella1.REGOUT
q[2] <= counter_cella2.REGOUT
q[3] <= counter_cella3.REGOUT
q[4] <= counter_cella4.REGOUT
sclr => counter_cella0.SCLR
sclr => counter_cella1.SCLR
sclr => counter_cella2.SCLR
sclr => counter_cella3.SCLR
sclr => counter_cella4.SCLR
updown => counter_cella0.DATAB
updown => counter_cella1.DATAB
updown => counter_cella2.DATAB
updown => counter_cella3.DATAB
updown => counter_cella4.DATAB


|lpm_fifo|fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|cntr_sua:wr_ptr
clock => counter_cella0.CLK
clock => counter_cella1.CLK
clock => counter_cella2.CLK
clock => counter_cella3.CLK
clock => counter_cella4.CLK
cnt_en => counter_cella0.DATAB
cnt_en => counter_cella1.DATAB
cnt_en => counter_cella2.DATAB
cnt_en => counter_cella3.DATAB
cnt_en => counter_cella4.DATAB
q[0] <= counter_cella0.REGOUT
q[1] <= counter_cella1.REGOUT
q[2] <= counter_cella2.REGOUT
q[3] <= counter_cella3.REGOUT
q[4] <= counter_cella4.REGOUT
sclr => counter_cella0.SCLR
sclr => counter_cella1.SCLR
sclr => counter_cella2.SCLR
sclr => counter_cella3.SCLR
sclr => counter_cella4.SCLR