lpm_fifo.hif

大量VHDL写的数字系统设计有用实例达到

Version 7.0 Build 33 02/05/2007 SJ Full Version
39
2288
OFF
OFF
OFF
OFF
ON
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Paths --
-- End Library Paths --
-- Start VHDL Libraries --
-- End VHDL Libraries --
# entity
lpm_fifo
# storage
db|lpm_fifo.(0).cnf
db|lpm_fifo.(0).cnf
# case_insensitive
# source_file
lpm_fifo.bdf
6715e6f80a26e8b1164556687b1f72
24
# hierarchies {
|
}
# end
# entity
fifo
# storage
db|lpm_fifo.(1).cnf
db|lpm_fifo.(1).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
fifo.vhd
2d8622e36a22f38575173f91be183a8
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
fifo:inst
}
# end
# entity
scfifo
# storage
db|lpm_fifo.(2).cnf
db|lpm_fifo.(2).cnf
# case_insensitive
# source_file
e:|altera|quartus ii7.0|quartus|libraries|megafunctions|scfifo.tdf
b595a49558d9be53086a660930ab77
6
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
lpm_width
8
PARAMETER_SIGNED_DEC
USR
LPM_NUMWORDS
32
PARAMETER_SIGNED_DEC
USR
LPM_WIDTHU
5
PARAMETER_SIGNED_DEC
USR
LPM_SHOWAHEAD
OFF
PARAMETER_UNKNOWN
USR
UNDERFLOW_CHECKING
ON
PARAMETER_UNKNOWN
USR
OVERFLOW_CHECKING
ON
PARAMETER_UNKNOWN
USR
ALLOW_RWCYCLE_WHEN_FULL
OFF
PARAMETER_UNKNOWN
DEF
ADD_RAM_OUTPUT_REGISTER
ON
PARAMETER_UNKNOWN
USR
ALMOST_FULL_VALUE
0
PARAMETER_UNKNOWN
DEF
ALMOST_EMPTY_VALUE
0
PARAMETER_UNKNOWN
DEF
USE_EAB
ON
PARAMETER_UNKNOWN
USR
MAXIMIZE_SPEED
5
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Stratix
PARAMETER_UNKNOWN
USR
OPTIMIZE_FOR_SPEED
5
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
scfifo_0mv
PARAMETER_UNKNOWN
USR
}
# used_port {
wrreq
-1
3
usedw4
-1
3
usedw3
-1
3
usedw2
-1
3
usedw1
-1
3
usedw0
-1
3
rdreq
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
full
-1
3
empty
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data3
-1
3
data2
-1
3
data1
-1
3
data0
-1
3
clock
-1
3
}
# include_file {
e:|altera|quartus ii7.0|quartus|libraries|megafunctions|a_dpfifo.inc
748303753a041187a5d4113b5f62acf
e:|altera|quartus ii7.0|quartus|libraries|megafunctions|a_regfifo.inc
afe6bfc54c15224ce61beaea9e71dc
e:|altera|quartus ii7.0|quartus|libraries|megafunctions|a_i2fifo.inc
ca5bb76c5a51df22b24c8b01cbcc918
e:|altera|quartus ii7.0|quartus|libraries|megafunctions|a_fffifo.inc
ebf62e69b8fb10b5db33a57861298d55
e:|altera|quartus ii7.0|quartus|libraries|megafunctions|a_f2fifo.inc
9bc132bd4e9e2ef1fb9633f6a742f
e:|altera|quartus ii7.0|quartus|libraries|megafunctions|aglobal70.inc
6e323611d63cddcc66b682e7ab39d4b7
}
# hierarchies {
fifo:inst|scfifo:scfifo_component
}
# end
# entity
scfifo_0mv
# storage
db|lpm_fifo.(3).cnf
db|lpm_fifo.(3).cnf
# case_insensitive
# source_file
db|scfifo_0mv.tdf
7b903066f71ba2df35bf5e9473e2879
6
# used_port {
wrreq
-1
3
usedw4
-1
3
usedw3
-1
3
usedw2
-1
3
usedw1
-1
3
usedw0
-1
3
rdreq
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
full
-1
3
empty
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data3
-1
3
data2
-1
3
data1
-1
3
data0
-1
3
clock
-1
3
}
# hierarchies {
fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated
}
# end
# entity
a_dpfifo_7sv
# storage
db|lpm_fifo.(4).cnf
db|lpm_fifo.(4).cnf
# case_insensitive
# source_file
db|a_dpfifo_7sv.tdf
481e57edcb124dd7540cc8113eeb134
6
# used_port {
wreq
-1
3
usedw4
-1
3
usedw3
-1
3
usedw2
-1
3
usedw1
-1
3
usedw0
-1
3
sclr
-1
3
rreq
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
full
-1
3
empty
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data3
-1
3
data2
-1
3
data1
-1
3
data0
-1
3
clock
-1
3
}
# hierarchies {
fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo
}
# end
# entity
altsyncram_qla1
# storage
db|lpm_fifo.(5).cnf
db|lpm_fifo.(5).cnf
# case_insensitive
# source_file
db|altsyncram_qla1.tdf
4a9d81ef6cb0673c8e52e0a83ad07a
6
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
wren_a
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b3
-1
3
q_b2
-1
3
q_b1
-1
3
q_b0
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a3
-1
3
data_a2
-1
3
data_a1
-1
3
data_a0
-1
3
clocken1
-1
3
clock1
-1
3
clock0
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# hierarchies {
fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|altsyncram_qla1:FIFOram
}
# end
# entity
cntr_rua
# storage
db|lpm_fifo.(6).cnf
db|lpm_fifo.(6).cnf
# case_insensitive
# source_file
db|cntr_rua.tdf
28473c88fa6a4e423e15975215a17791
6
# used_port {
sclr
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
cnt_en
-1
3
clock
-1
3
}
# hierarchies {
fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|cntr_rua:rd_ptr_msb
}
# end
# entity
cntr_8v6
# storage
db|lpm_fifo.(7).cnf
db|lpm_fifo.(7).cnf
# case_insensitive
# source_file
db|cntr_8v6.tdf
9f8e432113bc18d462d73e845d2c33
6
# used_port {
updown
-1
3
sclr
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
cnt_en
-1
3
clock
-1
3
}
# hierarchies {
fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|cntr_8v6:usedw_counter
}
# end
# entity
cntr_sua
# storage
db|lpm_fifo.(8).cnf
db|lpm_fifo.(8).cnf
# case_insensitive
# source_file
db|cntr_sua.tdf
83c3715f7986f784664b097f27bd040
6
# used_port {
sclr
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
cnt_en
-1
3
clock
-1
3
}
# hierarchies {
fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|cntr_sua:wr_ptr
}
# end
# complete