📄 lpm_fifo.tan.qmsg

📁 大量VHDL写的数字系统设计有用实例达到
💻 QMSG
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{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clock register fifo:inst\|scfifo:scfifo_component\|scfifo_0mv:auto_generated\|a_dpfifo_7sv:dpfifo\|empty_dff register fifo:inst\|scfifo:scfifo_component\|scfifo_0mv:auto_generated\|a_dpfifo_7sv:dpfifo\|empty_dff 314.86 MHz 3.176 ns Internal " "Info: Clock \"clock\" has Internal fmax of 314.86 MHz between source register \"fifo:inst\|scfifo:scfifo_component\|scfifo_0mv:auto_generated\|a_dpfifo_7sv:dpfifo\|empty_dff\" and destination register \"fifo:inst\|scfifo:scfifo_component\|scfifo_0mv:auto_generated\|a_dpfifo_7sv:dpfifo\|empty_dff\" (period= 3.176 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.010 ns + Longest register register " "Info: + Longest register to register delay is 3.010 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns fifo:inst\|scfifo:scfifo_component\|scfifo_0mv:auto_generated\|a_dpfifo_7sv:dpfifo\|empty_dff 1 REG LC_X21_Y23_N0 15 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X21_Y23_N0; Fanout = 15; REG Node = 'fifo:inst\|scfifo:scfifo_component\|scfifo_0mv:auto_generated\|a_dpfifo_7sv:dpfifo\|empty_dff'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|empty_dff } "NODE_NAME" } } { "db/a_dpfifo_7sv.tdf" "" { Text "D:/my_eda2/lpm_fifo/db/a_dpfifo_7sv.tdf" 44 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.004 ns) + CELL(0.183 ns) 1.187 ns fifo:inst\|scfifo:scfifo_component\|scfifo_0mv:auto_generated\|a_dpfifo_7sv:dpfifo\|_~404 2 COMB LC_X22_Y24_N5 2 " "Info: 2: + IC(1.004 ns) + CELL(0.183 ns) = 1.187 ns; Loc. = LC_X22_Y24_N5; Fanout = 2; COMB Node = 'fifo:inst\|scfifo:scfifo_component\|scfifo_0mv:auto_generated\|a_dpfifo_7sv:dpfifo\|_~404'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.187 ns" { fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|empty_dff fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|_~404 } "NODE_NAME" } } { "db/scfifo_0mv.tdf" "" { Text "D:/my_eda2/lpm_fifo/db/scfifo_0mv.tdf" 36 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.989 ns) + CELL(0.183 ns) 2.359 ns fifo:inst\|scfifo:scfifo_component\|scfifo_0mv:auto_generated\|a_dpfifo_7sv:dpfifo\|usedw_will_be_1~1 3 COMB LC_X21_Y23_N5 1 " "Info: 3: + IC(0.989 ns) + CELL(0.183 ns) = 2.359 ns; Loc. = LC_X21_Y23_N5; Fanout = 1; COMB Node = 'fifo:inst\|scfifo:scfifo_component\|scfifo_0mv:auto_generated\|a_dpfifo_7sv:dpfifo\|usedw_will_be_1~1'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.172 ns" { fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|_~404 fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|usedw_will_be_1~1 } "NODE_NAME" } } { "db/a_dpfifo_7sv.tdf" "" { Text "D:/my_eda2/lpm_fifo/db/a_dpfifo_7sv.tdf" 73 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.332 ns) + CELL(0.319 ns) 3.010 ns fifo:inst\|scfifo:scfifo_component\|scfifo_0mv:auto_generated\|a_dpfifo_7sv:dpfifo\|empty_dff 4 REG LC_X21_Y23_N0 15 " "Info: 4: + IC(0.332 ns) + CELL(0.319 ns) = 3.010 ns; Loc. = LC_X21_Y23_N0; Fanout = 15; REG Node = 'fifo:inst\|scfifo:scfifo_component\|scfifo_0mv:auto_generated\|a_dpfifo_7sv:dpfifo\|empty_dff'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.651 ns" { fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|usedw_will_be_1~1 fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|empty_dff } "NODE_NAME" } } { "db/a_dpfifo_7sv.tdf" "" { Text "D:/my_eda2/lpm_fifo/db/a_dpfifo_7sv.tdf" 44 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.685 ns ( 22.76 % ) " "Info: Total cell delay = 0.685 ns ( 22.76 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.325 ns ( 77.24 % ) " "Info: Total interconnect delay = 2.325 ns ( 77.24 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "3.010 ns" { fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|empty_dff fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|_~404 fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|usedw_will_be_1~1 fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|empty_dff } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "3.010 ns" { fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|empty_dff fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|_~404 fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|usedw_will_be_1~1 fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|empty_dff } { 0.000ns 1.004ns 0.989ns 0.332ns } { 0.000ns 0.183ns 0.183ns 0.319ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 2.936 ns + Shortest register " "Info: + Shortest clock path from clock \"clock\" to destination register is 2.936 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clock 1 CLK PIN_M20 59 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 59; CLK Node = 'clock'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "lpm_fifo.bdf" "" { Schematic "D:/my_eda2/lpm_fifo/lpm_fifo.bdf" { { 176 56 224 192 "clock" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.566 ns) + CELL(0.542 ns) 2.936 ns fifo:inst\|scfifo:scfifo_component\|scfifo_0mv:auto_generated\|a_dpfifo_7sv:dpfifo\|empty_dff 2 REG LC_X21_Y23_N0 15 " "Info: 2: + IC(1.566 ns) + CELL(0.542 ns) = 2.936 ns; Loc. = LC_X21_Y23_N0; Fanout = 15; REG Node = 'fifo:inst\|scfifo:scfifo_component\|scfifo_0mv:auto_generated\|a_dpfifo_7sv:dpfifo\|empty_dff'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.108 ns" { clock fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|empty_dff } "NODE_NAME" } } { "db/a_dpfifo_7sv.tdf" "" { Text "D:/my_eda2/lpm_fifo/db/a_dpfifo_7sv.tdf" 44 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 46.66 % ) " "Info: Total cell delay = 1.370 ns ( 46.66 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.566 ns ( 53.34 % ) " "Info: Total interconnect delay = 1.566 ns ( 53.34 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.936 ns" { clock fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|empty_dff } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.936 ns" { clock clock~out0 fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|empty_dff } { 0.000ns 0.000ns 1.566ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 2.936 ns - Longest register " "Info: - Longest clock path from clock \"clock\" to source register is 2.936 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clock 1 CLK PIN_M20 59 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 59; CLK Node = 'clock'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "lpm_fifo.bdf" "" { Schematic "D:/my_eda2/lpm_fifo/lpm_fifo.bdf" { { 176 56 224 192 "clock" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.566 ns) + CELL(0.542 ns) 2.936 ns fifo:inst\|scfifo:scfifo_component\|scfifo_0mv:auto_generated\|a_dpfifo_7sv:dpfifo\|empty_dff 2 REG LC_X21_Y23_N0 15 " "Info: 2: + IC(1.566 ns) + CELL(0.542 ns) = 2.936 ns; Loc. = LC_X21_Y23_N0; Fanout = 15; REG Node = 'fifo:inst\|scfifo:scfifo_component\|scfifo_0mv:auto_generated\|a_dpfifo_7sv:dpfifo\|empty_dff'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.108 ns" { clock fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|empty_dff } "NODE_NAME" } } { "db/a_dpfifo_7sv.tdf" "" { Text "D:/my_eda2/lpm_fifo/db/a_dpfifo_7sv.tdf" 44 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 46.66 % ) " "Info: Total cell delay = 1.370 ns ( 46.66 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.566 ns ( 53.34 % ) " "Info: Total interconnect delay = 1.566 ns ( 53.34 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.936 ns" { clock fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|empty_dff } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.936 ns" { clock clock~out0 fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|empty_dff } { 0.000ns 0.000ns 1.566ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.936 ns" { clock fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|empty_dff } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.936 ns" { clock clock~out0 fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|empty_dff } { 0.000ns 0.000ns 1.566ns } { 0.000ns 0.828ns 0.542ns } "" } } { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.936 ns" { clock fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|empty_dff } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.936 ns" { clock clock~out0 fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|empty_dff } { 0.000ns 0.000ns 1.566ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "db/a_dpfifo_7sv.tdf" "" { Text "D:/my_eda2/lpm_fifo/db/a_dpfifo_7sv.tdf" 44 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "db/a_dpfifo_7sv.tdf" "" { Text "D:/my_eda2/lpm_fifo/db/a_dpfifo_7sv.tdf" 44 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "3.010 ns" { fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|empty_dff fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|_~404 fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|usedw_will_be_1~1 fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|empty_dff } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "3.010 ns" { fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|empty_dff fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|_~404 fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|usedw_will_be_1~1 fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|empty_dff } { 0.000ns 1.004ns 0.989ns 0.332ns } { 0.000ns 0.183ns 0.183ns 0.319ns } "" } } { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.936 ns" { clock fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|empty_dff } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.936 ns" { clock clock~out0 fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|empty_dff } { 0.000ns 0.000ns 1.566ns } { 0.000ns 0.828ns 0.542ns } "" } } { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.936 ns" { clock fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|empty_dff } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.936 ns" { clock clock~out0 fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|empty_dff } { 0.000ns 0.000ns 1.566ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "fifo:inst\|scfifo:scfifo_component\|scfifo_0mv:auto_generated\|a_dpfifo_7sv:dpfifo\|empty_dff wrreq clock 4.851 ns register " "Info: tsu for register \"fifo:inst\|scfifo:scfifo_component\|scfifo_0mv:auto_generated\|a_dpfifo_7sv:dpfifo\|empty_dff\" (data pin = \"wrreq\", clock pin = \"clock\") is 4.851 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.777 ns + Longest pin register " "Info: + Longest pin to register delay is 7.777 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns wrreq 1 PIN PIN_C14 5 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_C14; Fanout = 5; PIN Node = 'wrreq'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { wrreq } "NODE_NAME" } } { "lpm_fifo.bdf" "" { Schematic "D:/my_eda2/lpm_fifo/lpm_fifo.bdf" { { 128 56 224 144 "wrreq" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.066 ns) + CELL(0.280 ns) 5.433 ns fifo:inst\|scfifo:scfifo_component\|scfifo_0mv:auto_generated\|a_dpfifo_7sv:dpfifo\|valid_wreq 2 COMB LC_X22_Y23_N5 16 " "Info: 2: + IC(4.066 ns) + CELL(0.280 ns) = 5.433 ns; Loc. = LC_X22_Y23_N5; Fanout = 16; COMB Node = 'fifo:inst\|scfifo:scfifo_component\|scfifo_0mv:auto_generated\|a_dpfifo_7sv:dpfifo\|valid_wreq'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "4.346 ns" { wrreq fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|valid_wreq } "NODE_NAME" } } { "db/a_dpfifo_7sv.tdf" "" { Text "D:/my_eda2/lpm_fifo/db/a_dpfifo_7sv.tdf" 75 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.822 ns) + CELL(0.183 ns) 6.438 ns fifo:inst\|scfifo:scfifo_component\|scfifo_0mv:auto_generated\|a_dpfifo_7sv:dpfifo\|usedw_will_be_1~57 3 COMB LC_X21_Y23_N3 2 " "Info: 3: + IC(0.822 ns) + CELL(0.183 ns) = 6.438 ns; Loc. = LC_X21_Y23_N3; Fanout = 2; COMB Node = 'fifo:inst\|scfifo:scfifo_component\|scfifo_0mv:auto_generated\|a_dpfifo_7sv:dpfifo\|usedw_will_be_1~57'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.005 ns" { fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|valid_wreq fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|usedw_will_be_1~57 } "NODE_NAME" } } { "db/a_dpfifo_7sv.tdf" "" { Text "D:/my_eda2/lpm_fifo/db/a_dpfifo_7sv.tdf" 73 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.322 ns) + CELL(0.366 ns) 7.126 ns fifo:inst\|scfifo:scfifo_component\|scfifo_0mv:auto_generated\|a_dpfifo_7sv:dpfifo\|usedw_will_be_1~1 4 COMB LC_X21_Y23_N5 1 " "Info: 4: + IC(0.322 ns) + CELL(0.366 ns) = 7.126 ns; Loc. = LC_X21_Y23_N5; Fanout = 1; COMB Node = 'fifo:inst\|scfifo:scfifo_component\|scfifo_0mv:auto_generated\|a_dpfifo_7sv:dpfifo\|usedw_will_be_1~1'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.688 ns" { fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|usedw_will_be_1~57 fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|usedw_will_be_1~1 } "NODE_NAME" } } { "db/a_dpfifo_7sv.tdf" "" { Text "D:/my_eda2/lpm_fifo/db/a_dpfifo_7sv.tdf" 73 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.332 ns) + CELL(0.319 ns) 7.777 ns fifo:inst\|scfifo:scfifo_component\|scfifo_0mv:auto_generated\|a_dpfifo_7sv:dpfifo\|empty_dff 5 REG LC_X21_Y23_N0 15 " "Info: 5: + IC(0.332 ns) + CELL(0.319 ns) = 7.777 ns; Loc. = LC_X21_Y23_N0; Fanout = 15; REG Node = 'fifo:inst\|scfifo:scfifo_component\|scfifo_0mv:auto_generated\|a_dpfifo_7sv:dpfifo\|empty_dff'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.651 ns" { fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|usedw_will_be_1~1 fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|empty_dff } "NODE_NAME" } } { "db/a_dpfifo_7sv.tdf" "" { Text "D:/my_eda2/lpm_fifo/db/a_dpfifo_7sv.tdf" 44 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.235 ns ( 28.74 % ) " "Info: Total cell delay = 2.235 ns ( 28.74 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.542 ns ( 71.26 % ) " "Info: Total interconnect delay = 5.542 ns ( 71.26 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "7.777 ns" { wrreq fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|valid_wreq fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|usedw_will_be_1~57 fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|usedw_will_be_1~1 fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|empty_dff } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "7.777 ns" { wrreq wrreq~out0 fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|valid_wreq fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|usedw_will_be_1~57 fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|usedw_will_be_1~1 fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|empty_dff } { 0.000ns 0.000ns 4.066ns 0.822ns 0.322ns 0.332ns } { 0.000ns 1.087ns 0.280ns 0.183ns 0.366ns 0.319ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "db/a_dpfifo_7sv.tdf" "" { Text "D:/my_eda2/lpm_fifo/db/a_dpfifo_7sv.tdf" 44 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 2.936 ns - Shortest register " "Info: - Shortest clock path from clock \"clock\" to destination register is 2.936 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clock 1 CLK PIN_M20 59 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 59; CLK Node = 'clock'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "lpm_fifo.bdf" "" { Schematic "D:/my_eda2/lpm_fifo/lpm_fifo.bdf" { { 176 56 224 192 "clock" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.566 ns) + CELL(0.542 ns) 2.936 ns fifo:inst\|scfifo:scfifo_component\|scfifo_0mv:auto_generated\|a_dpfifo_7sv:dpfifo\|empty_dff 2 REG LC_X21_Y23_N0 15 " "Info: 2: + IC(1.566 ns) + CELL(0.542 ns) = 2.936 ns; Loc. = LC_X21_Y23_N0; Fanout = 15; REG Node = 'fifo:inst\|scfifo:scfifo_component\|scfifo_0mv:auto_generated\|a_dpfifo_7sv:dpfifo\|empty_dff'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.108 ns" { clock fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|empty_dff } "NODE_NAME" } } { "db/a_dpfifo_7sv.tdf" "" { Text "D:/my_eda2/lpm_fifo/db/a_dpfifo_7sv.tdf" 44 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 46.66 % ) " "Info: Total cell delay = 1.370 ns ( 46.66 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.566 ns ( 53.34 % ) " "Info: Total interconnect delay = 1.566 ns ( 53.34 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.936 ns" { clock fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|empty_dff } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.936 ns" { clock clock~out0 fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|empty_dff } { 0.000ns 0.000ns 1.566ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "7.777 ns" { wrreq fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|valid_wreq fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|usedw_will_be_1~57 fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|usedw_will_be_1~1 fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|empty_dff } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "7.777 ns" { wrreq wrreq~out0 fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|valid_wreq fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|usedw_will_be_1~57 fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|usedw_will_be_1~1 fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|empty_dff } { 0.000ns 0.000ns 4.066ns 0.822ns 0.322ns 0.332ns } { 0.000ns 1.087ns 0.280ns 0.183ns 0.366ns 0.319ns } "" } } { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.936 ns" { clock fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|empty_dff } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.936 ns" { clock clock~out0 fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|empty_dff } { 0.000ns 0.000ns 1.566ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clock q\[0\] fifo:inst\|scfifo:scfifo_component\|scfifo_0mv:auto_generated\|a_dpfifo_7sv:dpfifo\|altsyncram_qla1:FIFOram\|q_b\[0\] 7.951 ns memory " "Info: tco from clock \"clock\" to destination pin \"q\[0\]\" through memory \"fifo:inst\|scfifo:scfifo_component\|scfifo_0mv:auto_generated\|a_dpfifo_7sv:dpfifo\|altsyncram_qla1:FIFOram\|q_b\[0\]\" is 7.951 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 2.723 ns + Longest memory " "Info: + Longest clock path from clock \"clock\" to source memory is 2.723 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clock 1 CLK PIN_M20 59 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 59; CLK Node = 'clock'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "lpm_fifo.bdf" "" { Schematic "D:/my_eda2/lpm_fifo/lpm_fifo.bdf" { { 176 56 224 192 "clock" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.560 ns) + CELL(0.335 ns) 2.723 ns fifo:inst\|scfifo:scfifo_component\|scfifo_0mv:auto_generated\|a_dpfifo_7sv:dpfifo\|altsyncram_qla1:FIFOram\|q_b\[0\] 2 MEM M512_X20_Y24 1 " "Info: 2: + IC(1.560 ns) + CELL(0.335 ns) = 2.723 ns; Loc. = M512_X20_Y24; Fanout = 1; MEM Node = 'fifo:inst\|scfifo:scfifo_component\|scfifo_0mv:auto_generated\|a_dpfifo_7sv:dpfifo\|altsyncram_qla1:FIFOram\|q_b\[0\]'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.895 ns" { clock fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|altsyncram_qla1:FIFOram|q_b[0] } "NODE_NAME" } } { "db/altsyncram_qla1.tdf" "" { Text "D:/my_eda2/lpm_fifo/db/altsyncram_qla1.tdf" 44 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.163 ns ( 42.71 % ) " "Info: Total cell delay = 1.163 ns ( 42.71 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.560 ns ( 57.29 % ) " "Info: Total interconnect delay = 1.560 ns ( 57.29 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.723 ns" { clock fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|altsyncram_qla1:FIFOram|q_b[0] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.723 ns" { clock clock~out0 fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|altsyncram_qla1:FIFOram|q_b[0] } { 0.000ns 0.000ns 1.560ns } { 0.000ns 0.828ns 0.335ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.519 ns + " "Info: + Micro clock to output delay of source is 0.519 ns" {  } { { "db/altsyncram_qla1.tdf" "" { Text "D:/my_eda2/lpm_fifo/db/altsyncram_qla1.tdf" 44 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.709 ns + Longest memory pin " "Info: + Longest memory to pin delay is 4.709 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.089 ns) 0.089 ns fifo:inst\|scfifo:scfifo_component\|scfifo_0mv:auto_generated\|a_dpfifo_7sv:dpfifo\|altsyncram_qla1:FIFOram\|q_b\[0\] 1 MEM M512_X20_Y24 1 " "Info: 1: + IC(0.000 ns) + CELL(0.089 ns) = 0.089 ns; Loc. = M512_X20_Y24; Fanout = 1; MEM Node = 'fifo:inst\|scfifo:scfifo_component\|scfifo_0mv:auto_generated\|a_dpfifo_7sv:dpfifo\|altsyncram_qla1:FIFOram\|q_b\[0\]'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|altsyncram_qla1:FIFOram|q_b[0] } "NODE_NAME" } } { "db/altsyncram_qla1.tdf" "" { Text "D:/my_eda2/lpm_fifo/db/altsyncram_qla1.tdf" 44 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.216 ns) + CELL(2.404 ns) 4.709 ns q\[0\] 2 PIN PIN_P14 0 " "Info: 2: + IC(2.216 ns) + CELL(2.404 ns) = 4.709 ns; Loc. = PIN_P14; Fanout = 0; PIN Node = 'q\[0\]'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "4.620 ns" { fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|altsyncram_qla1:FIFOram|q_b[0] q[0] } "NODE_NAME" } } { "lpm_fifo.bdf" "" { Schematic "D:/my_eda2/lpm_fifo/lpm_fifo.bdf" { { 104 464 640 120 "q\[7..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.493 ns ( 52.94 % ) " "Info: Total cell delay = 2.493 ns ( 52.94 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.216 ns ( 47.06 % ) " "Info: Total interconnect delay = 2.216 ns ( 47.06 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "4.709 ns" { fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|altsyncram_qla1:FIFOram|q_b[0] q[0] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "4.709 ns" { fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|altsyncram_qla1:FIFOram|q_b[0] q[0] } { 0.000ns 2.216ns } { 0.089ns 2.404ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.723 ns" { clock fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|altsyncram_qla1:FIFOram|q_b[0] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.723 ns" { clock clock~out0 fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|altsyncram_qla1:FIFOram|q_b[0] } { 0.000ns 0.000ns 1.560ns } { 0.000ns 0.828ns 0.335ns } "" } } { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "4.709 ns" { fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|altsyncram_qla1:FIFOram|q_b[0] q[0] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "4.709 ns" { fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|altsyncram_qla1:FIFOram|q_b[0] q[0] } { 0.000ns 2.216ns } { 0.089ns 2.404ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "fifo:inst\|scfifo:scfifo_component\|scfifo_0mv:auto_generated\|a_dpfifo_7sv:dpfifo\|altsyncram_qla1:FIFOram\|ram_block1a7~porta_datain_reg1 data\[6\] clock -2.345 ns memory " "Info: th for memory \"fifo:inst\|scfifo:scfifo_component\|scfifo_0mv:auto_generated\|a_dpfifo_7sv:dpfifo\|altsyncram_qla1:FIFOram\|ram_block1a7~porta_datain_reg1\" (data pin = \"data\[6\]\", clock pin = \"clock\") is -2.345 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 2.718 ns + Longest memory " "Info: + Longest clock path from clock \"clock\" to destination memory is 2.718 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clock 1 CLK PIN_M20 59 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 59; CLK Node = 'clock'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "lpm_fifo.bdf" "" { Schematic "D:/my_eda2/lpm_fifo/lpm_fifo.bdf" { { 176 56 224 192 "clock" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.560 ns) + CELL(0.330 ns) 2.718 ns fifo:inst\|scfifo:scfifo_component\|scfifo_0mv:auto_generated\|a_dpfifo_7sv:dpfifo\|altsyncram_qla1:FIFOram\|ram_block1a7~porta_datain_reg1 2 MEM M512_X20_Y24 1 " "Info: 2: + IC(1.560 ns) + CELL(0.330 ns) = 2.718 ns; Loc. = M512_X20_Y24; Fanout = 1; MEM Node = 'fifo:inst\|scfifo:scfifo_component\|scfifo_0mv:auto_generated\|a_dpfifo_7sv:dpfifo\|altsyncram_qla1:FIFOram\|ram_block1a7~porta_datain_reg1'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.890 ns" { clock fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|altsyncram_qla1:FIFOram|ram_block1a7~porta_datain_reg1 } "NODE_NAME" } } { "db/altsyncram_qla1.tdf" "" { Text "D:/my_eda2/lpm_fifo/db/altsyncram_qla1.tdf" 265 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.158 ns ( 42.60 % ) " "Info: Total cell delay = 1.158 ns ( 42.60 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.560 ns ( 57.40 % ) " "Info: Total interconnect delay = 1.560 ns ( 57.40 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.718 ns" { clock fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|altsyncram_qla1:FIFOram|ram_block1a7~porta_datain_reg1 } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.718 ns" { clock clock~out0 fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|altsyncram_qla1:FIFOram|ram_block1a7~porta_datain_reg1 } { 0.000ns 0.000ns 1.560ns } { 0.000ns 0.828ns 0.330ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.034 ns + " "Info: + Micro hold delay of destination is 0.034 ns" {  } { { "db/altsyncram_qla1.tdf" "" { Text "D:/my_eda2/lpm_fifo/db/altsyncram_qla1.tdf" 265 2 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.097 ns - Shortest pin memory " "Info: - Shortest pin to memory delay is 5.097 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.972 ns) 0.972 ns data\[6\] 1 PIN PIN_E13 1 " "Info: 1: + IC(0.000 ns) + CELL(0.972 ns) = 0.972 ns; Loc. = PIN_E13; Fanout = 1; PIN Node = 'data\[6\]'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { data[6] } "NODE_NAME" } } { "lpm_fifo.bdf" "" { Schematic "D:/my_eda2/lpm_fifo/lpm_fifo.bdf" { { 104 56 224 120 "data\[7..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.853 ns) + CELL(0.272 ns) 5.097 ns fifo:inst\|scfifo:scfifo_component\|scfifo_0mv:auto_generated\|a_dpfifo_7sv:dpfifo\|altsyncram_qla1:FIFOram\|ram_block1a7~porta_datain_reg1 2 MEM M512_X20_Y24 1 " "Info: 2: + IC(3.853 ns) + CELL(0.272 ns) = 5.097 ns; Loc. = M512_X20_Y24; Fanout = 1; MEM Node = 'fifo:inst\|scfifo:scfifo_component\|scfifo_0mv:auto_generated\|a_dpfifo_7sv:dpfifo\|altsyncram_qla1:FIFOram\|ram_block1a7~porta_datain_reg1'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "4.125 ns" { data[6] fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|altsyncram_qla1:FIFOram|ram_block1a7~porta_datain_reg1 } "NODE_NAME" } } { "db/altsyncram_qla1.tdf" "" { Text "D:/my_eda2/lpm_fifo/db/altsyncram_qla1.tdf" 265 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.244 ns ( 24.41 % ) " "Info: Total cell delay = 1.244 ns ( 24.41 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.853 ns ( 75.59 % ) " "Info: Total interconnect delay = 3.853 ns ( 75.59 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "5.097 ns" { data[6] fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|altsyncram_qla1:FIFOram|ram_block1a7~porta_datain_reg1 } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "5.097 ns" { data[6] data[6]~out0 fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|altsyncram_qla1:FIFOram|ram_block1a7~porta_datain_reg1 } { 0.000ns 0.000ns 3.853ns } { 0.000ns 0.972ns 0.272ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.718 ns" { clock fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|altsyncram_qla1:FIFOram|ram_block1a7~porta_datain_reg1 } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.718 ns" { clock clock~out0 fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|altsyncram_qla1:FIFOram|ram_block1a7~porta_datain_reg1 } { 0.000ns 0.000ns 1.560ns } { 0.000ns 0.828ns 0.330ns } "" } } { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "5.097 ns" { data[6] fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|altsyncram_qla1:FIFOram|ram_block1a7~porta_datain_reg1 } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "5.097 ns" { data[6] data[6]~out0 fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|altsyncram_qla1:FIFOram|ram_block1a7~porta_datain_reg1 } { 0.000ns 0.000ns 3.853ns } { 0.000ns 0.972ns 0.272ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
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