lpm_fifo.map.qmsg

大量VHDL写的数字系统设计有用实例达到

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.0 Build 33 02/05/2007 SJ Full Version " "Info: Version 7.0 Build 33 02/05/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Apr 23 16:19:08 2007 " "Info: Processing started: Mon Apr 23 16:19:08 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off lpm_fifo -c lpm_fifo " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off lpm_fifo -c lpm_fifo" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WSGN_MEGAFN_REPLACE" "lpm_fifo D:/my_eda2/lpm_fifo/lpm_fifo.bdf " "Warning: Entity \"lpm_fifo\" obtained from \"D:/my_eda2/lpm_fifo/lpm_fifo.bdf\" instead of from Quartus II megafunction library" {  } {  } 0 0 "Entity \"%1!s!\" obtained from \"%2!s!\" instead of from Quartus II megafunction library" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "lpm_fifo.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file lpm_fifo.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_fifo " "Info: Found entity 1: lpm_fifo" {  } { { "lpm_fifo.bdf" "" { Schematic "D:/my_eda2/lpm_fifo/lpm_fifo.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "lpm_fifo " "Info: Elaborating entity \"lpm_fifo\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "fifo.vhd 2 1 " "Warning: Using design file fifo.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 fifo-SYN " "Info: Found design unit 1: fifo-SYN" {  } { { "fifo.vhd" "" { Text "D:/my_eda2/lpm_fifo/fifo.vhd" 57 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 fifo " "Info: Found entity 1: fifo" {  } { { "fifo.vhd" "" { Text "D:/my_eda2/lpm_fifo/fifo.vhd" 42 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "fifo fifo:inst " "Info: Elaborating entity \"fifo\" for hierarchy \"fifo:inst\"" {  } { { "lpm_fifo.bdf" "inst" { Schematic "D:/my_eda2/lpm_fifo/lpm_fifo.bdf" { { 80 272 432 224 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/quartus ii7.0/quartus/libraries/megafunctions/scfifo.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus ii7.0/quartus/libraries/megafunctions/scfifo.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 scfifo " "Info: Found entity 1: scfifo" {  } { { "scfifo.tdf" "" { Text "e:/altera/quartus ii7.0/quartus/libraries/megafunctions/scfifo.tdf" 236 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "scfifo fifo:inst\|scfifo:scfifo_component " "Info: Elaborating entity \"scfifo\" for hierarchy \"fifo:inst\|scfifo:scfifo_component\"" {  } { { "fifo.vhd" "scfifo_component" { Text "D:/my_eda2/lpm_fifo/fifo.vhd" 97 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "fifo:inst\|scfifo:scfifo_component " "Info: Elaborated megafunction instantiation \"fifo:inst\|scfifo:scfifo_component\"" {  } { { "fifo.vhd" "" { Text "D:/my_eda2/lpm_fifo/fifo.vhd" 97 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/scfifo_0mv.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/scfifo_0mv.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 scfifo_0mv " "Info: Found entity 1: scfifo_0mv" {  } { { "db/scfifo_0mv.tdf" "" { Text "D:/my_eda2/lpm_fifo/db/scfifo_0mv.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "scfifo_0mv fifo:inst\|scfifo:scfifo_component\|scfifo_0mv:auto_generated " "Info: Elaborating entity \"scfifo_0mv\" for hierarchy \"fifo:inst\|scfifo:scfifo_component\|scfifo_0mv:auto_generated\"" {  } { { "scfifo.tdf" "auto_generated" { Text "e:/altera/quartus ii7.0/quartus/libraries/megafunctions/scfifo.tdf" 296 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_dpfifo_7sv.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/a_dpfifo_7sv.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_dpfifo_7sv " "Info: Found entity 1: a_dpfifo_7sv" {  } { { "db/a_dpfifo_7sv.tdf" "" { Text "D:/my_eda2/lpm_fifo/db/a_dpfifo_7sv.tdf" 30 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_dpfifo_7sv fifo:inst\|scfifo:scfifo_component\|scfifo_0mv:auto_generated\|a_dpfifo_7sv:dpfifo " "Info: Elaborating entity \"a_dpfifo_7sv\" for hierarchy \"fifo:inst\|scfifo:scfifo_component\|scfifo_0mv:auto_generated\|a_dpfifo_7sv:dpfifo\"" {  } { { "db/scfifo_0mv.tdf" "dpfifo" { Text "D:/my_eda2/lpm_fifo/db/scfifo_0mv.tdf" 36 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_qla1.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_qla1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_qla1 " "Info: Found entity 1: altsyncram_qla1" {  } { { "db/altsyncram_qla1.tdf" "" { Text "D:/my_eda2/lpm_fifo/db/altsyncram_qla1.tdf" 36 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_qla1 fifo:inst\|scfifo:scfifo_component\|scfifo_0mv:auto_generated\|a_dpfifo_7sv:dpfifo\|altsyncram_qla1:FIFOram " "Info: Elaborating entity \"altsyncram_qla1\" for hierarchy \"fifo:inst\|scfifo:scfifo_component\|scfifo_0mv:auto_generated\|a_dpfifo_7sv:dpfifo\|altsyncram_qla1:FIFOram\"" {  } { { "db/a_dpfifo_7sv.tdf" "FIFOram" { Text "D:/my_eda2/lpm_fifo/db/a_dpfifo_7sv.tdf" 43 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_rua.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_rua.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_rua " "Info: Found entity 1: cntr_rua" {  } { { "db/cntr_rua.tdf" "" { Text "D:/my_eda2/lpm_fifo/db/cntr_rua.tdf" 25 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_rua fifo:inst\|scfifo:scfifo_component\|scfifo_0mv:auto_generated\|a_dpfifo_7sv:dpfifo\|cntr_rua:rd_ptr_msb " "Info: Elaborating entity \"cntr_rua\" for hierarchy \"fifo:inst\|scfifo:scfifo_component\|scfifo_0mv:auto_generated\|a_dpfifo_7sv:dpfifo\|cntr_rua:rd_ptr_msb\"" {  } { { "db/a_dpfifo_7sv.tdf" "rd_ptr_msb" { Text "D:/my_eda2/lpm_fifo/db/a_dpfifo_7sv.tdf" 59 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_8v6.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_8v6.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_8v6 " "Info: Found entity 1: cntr_8v6" {  } { { "db/cntr_8v6.tdf" "" { Text "D:/my_eda2/lpm_fifo/db/cntr_8v6.tdf" 25 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_8v6 fifo:inst\|scfifo:scfifo_component\|scfifo_0mv:auto_generated\|a_dpfifo_7sv:dpfifo\|cntr_8v6:usedw_counter " "Info: Elaborating entity \"cntr_8v6\" for hierarchy \"fifo:inst\|scfifo:scfifo_component\|scfifo_0mv:auto_generated\|a_dpfifo_7sv:dpfifo\|cntr_8v6:usedw_counter\"" {  } { { "db/a_dpfifo_7sv.tdf" "usedw_counter" { Text "D:/my_eda2/lpm_fifo/db/a_dpfifo_7sv.tdf" 60 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_sua.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_sua.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_sua " "Info: Found entity 1: cntr_sua" {  } { { "db/cntr_sua.tdf" "" { Text "D:/my_eda2/lpm_fifo/db/cntr_sua.tdf" 25 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_sua fifo:inst\|scfifo:scfifo_component\|scfifo_0mv:auto_generated\|a_dpfifo_7sv:dpfifo\|cntr_sua:wr_ptr " "Info: Elaborating entity \"cntr_sua\" for hierarchy \"fifo:inst\|scfifo:scfifo_component\|scfifo_0mv:auto_generated\|a_dpfifo_7sv:dpfifo\|cntr_sua:wr_ptr\"" {  } { { "db/a_dpfifo_7sv.tdf" "wr_ptr" { Text "D:/my_eda2/lpm_fifo/db/a_dpfifo_7sv.tdf" 61 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "75 " "Info: Implemented 75 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "11 " "Info: Implemented 11 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "15 " "Info: Implemented 15 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "41 " "Info: Implemented 41 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0} { "Info" "ISCL_SCL_TM_RAMS" "8 " "Info: Implemented 8 RAM segments" {  } {  } 0 0 "Implemented %1!d! RAM segments" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 2 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "148 " "Info: Allocated 148 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon Apr 23 16:19:19 2007 " "Info: Processing ended: Mon Apr 23 16:19:19 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Info: Elapsed time: 00:00:11" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}