lpm_fifo.sim.qmsg

大量VHDL写的数字系统设计有用实例达到

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Simulator Quartus II " "Info: Running Quartus II Simulator" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.0 Build 33 02/05/2007 SJ Full Version " "Info: Version 7.0 Build 33 02/05/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Apr 23 17:28:01 2007 " "Info: Processing started: Mon Apr 23 17:28:01 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sim --read_settings_files=on --write_settings_files=off lpm_fifo -c lpm_fifo " "Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off lpm_fifo -c lpm_fifo" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISDB_SOURCE_VECTOR_FILE_USED" "D:/my_eda2/lpm_fifo/lpm_fifo.vwf " "Info: Using vector source file \"D:/my_eda2/lpm_fifo/lpm_fifo.vwf\"" {  } {  } 0 0 "Using vector source file \"%1!s!\"" 0 0}
{ "Info" "ISDB_OVERWRITE_WAVEFORM_INPUTS_WITH_SIMULATION_OUTPUTS" "" "Info: Overwriting simulation input file with simulation results" { { "Info" "ISDB_SOURCE_VECTOR_FILE_BACKUP" "lpm_fifo.vwf lpm_fifo.sim_ori.vwf " "Info: A backup of lpm_fifo.vwf called lpm_fifo.sim_ori.vwf has been created in the db folder" {  } {  } 0 0 "A backup of %1!s! called %2!s! has been created in the db folder" 0 0}  } {  } 0 0 "Overwriting simulation input file with simulation results" 0 0}
{ "Warning" "WSDB_YGR_YGR_AUTO_WRITE_ON_NEG_EDGE" "fifo:inst\|scfifo:scfifo_component\|scfifo_0mv:auto_generated\|a_dpfifo_7sv:dpfifo\|altsyncram_qla1:FIFOram\|ram_block1a0 " "Warning: Write to auto-size memory block \"fifo:inst\|scfifo:scfifo_component\|scfifo_0mv:auto_generated\|a_dpfifo_7sv:dpfifo\|altsyncram_qla1:FIFOram\|ram_block1a0\" assumed to occur on falling edge of input clock" {  } {  } 0 0 "Write to auto-size memory block \"%1!s!\" assumed to occur on falling edge of input clock" 0 0}
{ "Warning" "WSDB_YGR_YGR_AUTO_WRITE_ON_NEG_EDGE" "fifo:inst\|scfifo:scfifo_component\|scfifo_0mv:auto_generated\|a_dpfifo_7sv:dpfifo\|altsyncram_qla1:FIFOram\|ram_block1a1 " "Warning: Write to auto-size memory block \"fifo:inst\|scfifo:scfifo_component\|scfifo_0mv:auto_generated\|a_dpfifo_7sv:dpfifo\|altsyncram_qla1:FIFOram\|ram_block1a1\" assumed to occur on falling edge of input clock" {  } {  } 0 0 "Write to auto-size memory block \"%1!s!\" assumed to occur on falling edge of input clock" 0 0}
{ "Warning" "WSDB_YGR_YGR_AUTO_WRITE_ON_NEG_EDGE" "fifo:inst\|scfifo:scfifo_component\|scfifo_0mv:auto_generated\|a_dpfifo_7sv:dpfifo\|altsyncram_qla1:FIFOram\|ram_block1a2 " "Warning: Write to auto-size memory block \"fifo:inst\|scfifo:scfifo_component\|scfifo_0mv:auto_generated\|a_dpfifo_7sv:dpfifo\|altsyncram_qla1:FIFOram\|ram_block1a2\" assumed to occur on falling edge of input clock" {  } {  } 0 0 "Write to auto-size memory block \"%1!s!\" assumed to occur on falling edge of input clock" 0 0}
{ "Warning" "WSDB_YGR_YGR_AUTO_WRITE_ON_NEG_EDGE" "fifo:inst\|scfifo:scfifo_component\|scfifo_0mv:auto_generated\|a_dpfifo_7sv:dpfifo\|altsyncram_qla1:FIFOram\|ram_block1a3 " "Warning: Write to auto-size memory block \"fifo:inst\|scfifo:scfifo_component\|scfifo_0mv:auto_generated\|a_dpfifo_7sv:dpfifo\|altsyncram_qla1:FIFOram\|ram_block1a3\" assumed to occur on falling edge of input clock" {  } {  } 0 0 "Write to auto-size memory block \"%1!s!\" assumed to occur on falling edge of input clock" 0 0}
{ "Warning" "WSDB_YGR_YGR_AUTO_WRITE_ON_NEG_EDGE" "fifo:inst\|scfifo:scfifo_component\|scfifo_0mv:auto_generated\|a_dpfifo_7sv:dpfifo\|altsyncram_qla1:FIFOram\|ram_block1a4 " "Warning: Write to auto-size memory block \"fifo:inst\|scfifo:scfifo_component\|scfifo_0mv:auto_generated\|a_dpfifo_7sv:dpfifo\|altsyncram_qla1:FIFOram\|ram_block1a4\" assumed to occur on falling edge of input clock" {  } {  } 0 0 "Write to auto-size memory block \"%1!s!\" assumed to occur on falling edge of input clock" 0 0}
{ "Warning" "WSDB_YGR_YGR_AUTO_WRITE_ON_NEG_EDGE" "fifo:inst\|scfifo:scfifo_component\|scfifo_0mv:auto_generated\|a_dpfifo_7sv:dpfifo\|altsyncram_qla1:FIFOram\|ram_block1a5 " "Warning: Write to auto-size memory block \"fifo:inst\|scfifo:scfifo_component\|scfifo_0mv:auto_generated\|a_dpfifo_7sv:dpfifo\|altsyncram_qla1:FIFOram\|ram_block1a5\" assumed to occur on falling edge of input clock" {  } {  } 0 0 "Write to auto-size memory block \"%1!s!\" assumed to occur on falling edge of input clock" 0 0}
{ "Warning" "WSDB_YGR_YGR_AUTO_WRITE_ON_NEG_EDGE" "fifo:inst\|scfifo:scfifo_component\|scfifo_0mv:auto_generated\|a_dpfifo_7sv:dpfifo\|altsyncram_qla1:FIFOram\|ram_block1a6 " "Warning: Write to auto-size memory block \"fifo:inst\|scfifo:scfifo_component\|scfifo_0mv:auto_generated\|a_dpfifo_7sv:dpfifo\|altsyncram_qla1:FIFOram\|ram_block1a6\" assumed to occur on falling edge of input clock" {  } {  } 0 0 "Write to auto-size memory block \"%1!s!\" assumed to occur on falling edge of input clock" 0 0}
{ "Warning" "WSDB_YGR_YGR_AUTO_WRITE_ON_NEG_EDGE" "fifo:inst\|scfifo:scfifo_component\|scfifo_0mv:auto_generated\|a_dpfifo_7sv:dpfifo\|altsyncram_qla1:FIFOram\|ram_block1a7 " "Warning: Write to auto-size memory block \"fifo:inst\|scfifo:scfifo_component\|scfifo_0mv:auto_generated\|a_dpfifo_7sv:dpfifo\|altsyncram_qla1:FIFOram\|ram_block1a7\" assumed to occur on falling edge of input clock" {  } {  } 0 0 "Write to auto-size memory block \"%1!s!\" assumed to occur on falling edge of input clock" 0 0}
{ "Info" "IEDS_MAX_TRANSITION_COUNT" "" "Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled" { { "Info" "IEDS_MAX_TRANSITION_COUNT_EXP" "" "Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements." {  } {  } 0 0 "Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements." 0 0}  } {  } 0 0 "Option to preserve fewer signal transitions to reduce memory requirements is enabled" 0 0}
{ "Info" "IEDS_SUB_SIMULATION_COUNT" "1 " "Info: Simulation partitioned into 1 sub-simulations" {  } {  } 0 0 "Simulation partitioned into %1!d! sub-simulations" 0 0}
{ "Info" "ISIM_SIM_SIMULATION_COVERAGE" "     69.17 % " "Info: Simulation coverage is      69.17 %" {  } {  } 0 0 "Simulation coverage is %1!s!" 0 0}
{ "Info" "ISIM_SIM_NUMBER_OF_TRANSITION" "878 " "Info: Number of transitions in simulation is 878" {  } {  } 0 0 "Number of transitions in simulation is %1!s!" 0 0}
{ "Info" "ISDB_SDB_PROMOTE_WRITE_BINARY_VECTOR" "lpm_fifo.vwf " "Info: Vector file lpm_fifo.vwf is saved in VWF text format. You can compress it into CVWF format in order to reduce file size. For more details please refer to the Quartus II Help." {  } {  } 0 0 "Vector file %1!s! is saved in VWF text format. You can compress it into CVWF format in order to reduce file size. For more details please refer to the Quartus II Help." 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Simulator 0 s 8 s Quartus II " "Info: Quartus II Simulator was successful. 0 errors, 8 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "88 " "Info: Allocated 88 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon Apr 23 17:28:03 2007 " "Info: Processing ended: Mon Apr 23 17:28:03 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}