lpm_fifo.tan.rpt

大量VHDL写的数字系统设计有用实例达到

+------------------------------+-------+---------------+----------------------------------+----------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------+------------+----------+--------------+
; Worst-case tsu               ; N/A   ; None          ; 4.851 ns                         ; wrreq                                                                                                          ; fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|empty_dff                                              ; --         ; clock    ; 0            ;
; Worst-case tco               ; N/A   ; None          ; 7.951 ns                         ; fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|altsyncram_qla1:FIFOram|q_b[0] ; q[0]                                                                                                                                   ; clock      ; --       ; 0            ;
; Worst-case th                ; N/A   ; None          ; -2.345 ns                        ; data[6]                                                                                                        ; fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|altsyncram_qla1:FIFOram|ram_block1a7~porta_datain_reg1 ; --         ; clock    ; 0            ;
; Clock Setup: 'clock'         ; N/A   ; None          ; 314.86 MHz ( period = 3.176 ns ) ; fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|empty_dff                      ; fifo:inst|scfifo:scfifo_component|scfifo_0mv:auto_generated|a_dpfifo_7sv:dpfifo|empty_dff                                              ; clock      ; clock    ; 0            ;
; Total number of failed paths ;       ;               ;                                  ;                                                                                                                ;                                                                                                                                        ;            ;          ; 0            ;
+------------------------------+-------+---------------+----------------------------------+----------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1S10F484C5       ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clock           ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+