clock_1.sta.rpt

大量VHDL写的数字系统设计有用实例达到

TimeQuest Timing Analyzer report for clock_1
Sun May 13 15:37:14 2007
Quartus II Version 7.0 Build 33 02/05/2007 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. TimeQuest Timing Analyzer Summary
  3. SDC File List
  4. Clocks
  5. Unconstrained Paths
  6. TimeQuest Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+----------------------------------------------------------------------+
; TimeQuest Timing Analyzer Summary                                    ;
+--------------------+-------------------------------------------------+
; Quartus II Version ; Version 7.0 Build 33 02/05/2007 SJ Full Version ;
; Revision Name      ; clock_1                                         ;
; Device Family      ; Cyclone II                                      ;
; Device Name        ; EP2C8T144C8                                     ;
; Timing Models      ; Final                                           ;
; Delay Model        ; Slow Model                                      ;
; Rise/Fall Delays   ; Unavailable                                     ;
+--------------------+-------------------------------------------------+


+---------------------------------------------------+
; SDC File List                                     ;
+---------------+--------+--------------------------+
; SDC File Path ; Status ; Read at                  ;
+---------------+--------+--------------------------+
; clock_1.sdc   ; OK     ; Sun May 13 15:37:14 2007 ;
+---------------+--------+--------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clocks                                                                                                                                                                ;
+------------+---------+--------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------+
; Clock Name ; Type    ; Period ; Rise  ; Fall  ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ;
+------------+---------+--------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------+
; N/C        ; Virtual ; 10.000 ; 0.000 ; 5.000 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { }     ;
+------------+---------+--------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------+


+------------------------------------------------+
; Unconstrained Paths                            ;
+---------------------------------+-------+------+
; Property                        ; Setup ; Hold ;
+---------------------------------+-------+------+
; Illegal Clocks                  ; 0     ; 0    ;
; Unconstrained Clocks            ; 2     ; 2    ;
; Unconstrained Input Ports       ; 2     ; 2    ;
; Unconstrained Input Port Paths  ; 34    ; 34   ;
; Unconstrained Output Ports      ; 7     ; 7    ;
; Unconstrained Output Port Paths ; 140   ; 140  ;
+---------------------------------+-------+------+


+------------------------------------+
; TimeQuest Timing Analyzer Messages ;
+------------------------------------+
Info: *******************************************************************
Info: Running Quartus II TimeQuest Timing Analyzer
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Sun May 13 15:37:12 2007
Info: Command: quartus_sta clock_1 -c clock_1
Info: qsta_default_script.tcl version: 23.0.1.4
Info: Reading SDC File: 'clock_1.sdc'
Warning: Node: clk1hz was determined to be a clock but was found without an associated clock assignment.
Warning: Node: clk was determined to be a clock but was found without an associated clock assignment.
Warning: Command report_clock_fmax_summary could not find any constraints or exceptions to report
Info: No setup paths to report
Info: No hold paths to report
Info: No recovery paths to report
Info: No removal paths to report
Warning: Command report_min_pulse_width could not find any constraints or exceptions to report
Info: Design is not fully constrained for setup requirements
Info: Design is not fully constrained for hold requirements
Info: Quartus II TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings
    Info: Allocated 107 megabytes of memory during processing
    Info: Processing ended: Sun May 13 15:37:14 2007
    Info: Elapsed time: 00:00:02