cymometer.map.qmsg

大量VHDL写的数字系统设计有用实例达到

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.0 Build 33 02/05/2007 SJ Full Version " "Info: Version 7.0 Build 33 02/05/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Apr 09 20:32:51 2007 " "Info: Processing started: Mon Apr 09 20:32:51 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off cymometer -c cymometer " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off cymometer -c cymometer" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cymometer.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file cymometer.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 cymometer-one " "Info: Found design unit 1: cymometer-one" {  } { { "cymometer.vhd" "" { Text "D:/my_eda2/cymometer/cymometer.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 cymometer " "Info: Found entity 1: cymometer" {  } { { "cymometer.vhd" "" { Text "D:/my_eda2/cymometer/cymometer.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "cymometer " "Info: Elaborating entity \"cymometer\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "seg7 cymometer.vhd(77) " "Warning (10631): VHDL Process Statement warning at cymometer.vhd(77): inferring latch(es) for signal or variable \"seg7\", which holds its previous value in one or more paths through the process" {  } { { "cymometer.vhd" "" { Text "D:/my_eda2/cymometer/cymometer.vhd" 77 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "seg7\[0\] cymometer.vhd(77) " "Info (10041): Verilog HDL or VHDL info at cymometer.vhd(77): inferred latch for \"seg7\[0\]\"" {  } { { "cymometer.vhd" "" { Text "D:/my_eda2/cymometer/cymometer.vhd" 77 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "seg7\[1\] cymometer.vhd(77) " "Info (10041): Verilog HDL or VHDL info at cymometer.vhd(77): inferred latch for \"seg7\[1\]\"" {  } { { "cymometer.vhd" "" { Text "D:/my_eda2/cymometer/cymometer.vhd" 77 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "seg7\[2\] cymometer.vhd(77) " "Info (10041): Verilog HDL or VHDL info at cymometer.vhd(77): inferred latch for \"seg7\[2\]\"" {  } { { "cymometer.vhd" "" { Text "D:/my_eda2/cymometer/cymometer.vhd" 77 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "seg7\[3\] cymometer.vhd(77) " "Info (10041): Verilog HDL or VHDL info at cymometer.vhd(77): inferred latch for \"seg7\[3\]\"" {  } { { "cymometer.vhd" "" { Text "D:/my_eda2/cymometer/cymometer.vhd" 77 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "seg7\[4\] cymometer.vhd(77) " "Info (10041): Verilog HDL or VHDL info at cymometer.vhd(77): inferred latch for \"seg7\[4\]\"" {  } { { "cymometer.vhd" "" { Text "D:/my_eda2/cymometer/cymometer.vhd" 77 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "seg7\[5\] cymometer.vhd(77) " "Info (10041): Verilog HDL or VHDL info at cymometer.vhd(77): inferred latch for \"seg7\[5\]\"" {  } { { "cymometer.vhd" "" { Text "D:/my_eda2/cymometer/cymometer.vhd" 77 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "seg7\[6\] cymometer.vhd(77) " "Info (10041): Verilog HDL or VHDL info at cymometer.vhd(77): inferred latch for \"seg7\[6\]\"" {  } { { "cymometer.vhd" "" { Text "D:/my_eda2/cymometer/cymometer.vhd" 77 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "seg7\[0\]\$latch " "Warning: Latch seg7\[0\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA cnt\[13\] " "Warning: Ports D and ENA on the latch are fed by the same signal cnt\[13\]" {  } { { "cymometer.vhd" "" { Text "D:/my_eda2/cymometer/cymometer.vhd" 20 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "cymometer.vhd" "" { Text "D:/my_eda2/cymometer/cymometer.vhd" 77 0 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "seg7\[1\]\$latch " "Warning: Latch seg7\[1\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA cnt\[13\] " "Warning: Ports D and ENA on the latch are fed by the same signal cnt\[13\]" {  } { { "cymometer.vhd" "" { Text "D:/my_eda2/cymometer/cymometer.vhd" 20 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "cymometer.vhd" "" { Text "D:/my_eda2/cymometer/cymometer.vhd" 77 0 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "seg7\[2\]\$latch " "Warning: Latch seg7\[2\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA cnt\[13\] " "Warning: Ports D and ENA on the latch are fed by the same signal cnt\[13\]" {  } { { "cymometer.vhd" "" { Text "D:/my_eda2/cymometer/cymometer.vhd" 20 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "cymometer.vhd" "" { Text "D:/my_eda2/cymometer/cymometer.vhd" 77 0 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "seg7\[3\]\$latch " "Warning: Latch seg7\[3\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA cnt\[13\] " "Warning: Ports D and ENA on the latch are fed by the same signal cnt\[13\]" {  } { { "cymometer.vhd" "" { Text "D:/my_eda2/cymometer/cymometer.vhd" 20 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "cymometer.vhd" "" { Text "D:/my_eda2/cymometer/cymometer.vhd" 77 0 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "seg7\[4\]\$latch " "Warning: Latch seg7\[4\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA cnt\[13\] " "Warning: Ports D and ENA on the latch are fed by the same signal cnt\[13\]" {  } { { "cymometer.vhd" "" { Text "D:/my_eda2/cymometer/cymometer.vhd" 20 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "cymometer.vhd" "" { Text "D:/my_eda2/cymometer/cymometer.vhd" 77 0 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "seg7\[5\]\$latch " "Warning: Latch seg7\[5\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA cnt\[13\] " "Warning: Ports D and ENA on the latch are fed by the same signal cnt\[13\]" {  } { { "cymometer.vhd" "" { Text "D:/my_eda2/cymometer/cymometer.vhd" 20 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "cymometer.vhd" "" { Text "D:/my_eda2/cymometer/cymometer.vhd" 77 0 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "seg7\[6\]\$latch " "Warning: Latch seg7\[6\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA cnt\[13\] " "Warning: Ports D and ENA on the latch are fed by the same signal cnt\[13\]" {  } { { "cymometer.vhd" "" { Text "D:/my_eda2/cymometer/cymometer.vhd" 20 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "cymometer.vhd" "" { Text "D:/my_eda2/cymometer/cymometer.vhd" 77 0 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "218 " "Info: Implemented 218 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "15 " "Info: Implemented 15 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "201 " "Info: Implemented 201 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 15 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 15 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "141 " "Info: Allocated 141 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon Apr 09 20:32:55 2007 " "Info: Processing ended: Mon Apr 09 20:32:55 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}