cymometer.tan.qmsg

大量VHDL写的数字系统设计有用实例达到

{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off cymometer -c cymometer --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off cymometer -c cymometer --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "" "Warning: Timing Analysis is analyzing one or more combinational loops as latches" { { "Warning" "WTDB_COMB_LATCH_NODE" "seg7\[0\]\$latch " "Warning: Node \"seg7\[0\]\$latch\" is a latch" {  } { { "cymometer.vhd" "" { Text "D:/my_eda2/cymometer/cymometer.vhd" 77 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "seg7\[1\]\$latch " "Warning: Node \"seg7\[1\]\$latch\" is a latch" {  } { { "cymometer.vhd" "" { Text "D:/my_eda2/cymometer/cymometer.vhd" 77 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "seg7\[2\]\$latch " "Warning: Node \"seg7\[2\]\$latch\" is a latch" {  } { { "cymometer.vhd" "" { Text "D:/my_eda2/cymometer/cymometer.vhd" 77 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "seg7\[3\]\$latch " "Warning: Node \"seg7\[3\]\$latch\" is a latch" {  } { { "cymometer.vhd" "" { Text "D:/my_eda2/cymometer/cymometer.vhd" 77 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "seg7\[4\]\$latch " "Warning: Node \"seg7\[4\]\$latch\" is a latch" {  } { { "cymometer.vhd" "" { Text "D:/my_eda2/cymometer/cymometer.vhd" 77 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "seg7\[5\]\$latch " "Warning: Node \"seg7\[5\]\$latch\" is a latch" {  } { { "cymometer.vhd" "" { Text "D:/my_eda2/cymometer/cymometer.vhd" 77 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "seg7\[6\]\$latch " "Warning: Node \"seg7\[6\]\$latch\" is a latch" {  } { { "cymometer.vhd" "" { Text "D:/my_eda2/cymometer/cymometer.vhd" 77 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0}  } {  } 0 0 "Timing Analysis is analyzing one or more combinational loops as latches" 0 0}