lpm_ram.tan.qmsg

大量VHDL写的数字系统设计有用实例达到

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clock memory memory altsyncram:altsyncram_component\|altsyncram_03a1:auto_generated\|ram_block1a0~porta_we_reg altsyncram:altsyncram_component\|altsyncram_03a1:auto_generated\|q_a\[0\] 163.03 MHz Internal " "Info: Clock \"clock\" Internal fmax is restricted to 163.03 MHz between source memory \"altsyncram:altsyncram_component\|altsyncram_03a1:auto_generated\|ram_block1a0~porta_we_reg\" and destination memory \"altsyncram:altsyncram_component\|altsyncram_03a1:auto_generated\|q_a\[0\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "3.067 ns 3.067 ns 6.134 ns " "Info: fmax restricted to Clock High delay (3.067 ns) plus Clock Low delay (3.067 ns) : restricted to 6.134 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.641 ns + Longest memory memory " "Info: + Longest memory to memory delay is 3.641 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altsyncram:altsyncram_component\|altsyncram_03a1:auto_generated\|ram_block1a0~porta_we_reg 1 MEM M4K_X27_Y12 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X27_Y12; Fanout = 8; MEM Node = 'altsyncram:altsyncram_component\|altsyncram_03a1:auto_generated\|ram_block1a0~porta_we_reg'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_we_reg } "NODE_NAME" } } { "db/altsyncram_03a1.tdf" "" { Text "D:/my_eda2/lpm_ram/db/altsyncram_03a1.tdf" 45 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.641 ns) 3.641 ns altsyncram:altsyncram_component\|altsyncram_03a1:auto_generated\|q_a\[0\] 2 MEM M4K_X27_Y12 1 " "Info: 2: + IC(0.000 ns) + CELL(3.641 ns) = 3.641 ns; Loc. = M4K_X27_Y12; Fanout = 1; MEM Node = 'altsyncram:altsyncram_component\|altsyncram_03a1:auto_generated\|q_a\[0\]'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "3.641 ns" { altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_we_reg altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[0] } "NODE_NAME" } } { "db/altsyncram_03a1.tdf" "" { Text "D:/my_eda2/lpm_ram/db/altsyncram_03a1.tdf" 41 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.641 ns ( 100.00 % ) " "Info: Total cell delay = 3.641 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "3.641 ns" { altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_we_reg altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[0] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "3.641 ns" { altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_we_reg altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[0] } { 0.000ns 0.000ns } { 0.000ns 3.641ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.020 ns - Smallest " "Info: - Smallest clock skew is -0.020 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 2.873 ns + Shortest memory " "Info: + Shortest clock path from clock \"clock\" to destination memory is 2.873 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clock 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clock'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "lpm_ram.vhd" "" { Text "D:/my_eda2/lpm_ram/lpm_ram.vhd" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns clock~clkctrl 2 COMB CLKCTRL_G2 30 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 30; COMB Node = 'clock~clkctrl'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clock clock~clkctrl } "NODE_NAME" } } { "lpm_ram.vhd" "" { Text "D:/my_eda2/lpm_ram/lpm_ram.vhd" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.829 ns) + CELL(0.815 ns) 2.873 ns altsyncram:altsyncram_component\|altsyncram_03a1:auto_generated\|q_a\[0\] 3 MEM M4K_X27_Y12 1 " "Info: 3: + IC(0.829 ns) + CELL(0.815 ns) = 2.873 ns; Loc. = M4K_X27_Y12; Fanout = 1; MEM Node = 'altsyncram:altsyncram_component\|altsyncram_03a1:auto_generated\|q_a\[0\]'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.644 ns" { clock~clkctrl altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[0] } "NODE_NAME" } } { "db/altsyncram_03a1.tdf" "" { Text "D:/my_eda2/lpm_ram/db/altsyncram_03a1.tdf" 41 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.905 ns ( 66.31 % ) " "Info: Total cell delay = 1.905 ns ( 66.31 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.968 ns ( 33.69 % ) " "Info: Total interconnect delay = 0.968 ns ( 33.69 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.873 ns" { clock clock~clkctrl altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[0] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.873 ns" { clock clock~combout clock~clkctrl altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[0] } { 0.000ns 0.000ns 0.139ns 0.829ns } { 0.000ns 1.090ns 0.000ns 0.815ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 2.893 ns - Longest memory " "Info: - Longest clock path from clock \"clock\" to source memory is 2.893 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clock 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clock'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "lpm_ram.vhd" "" { Text "D:/my_eda2/lpm_ram/lpm_ram.vhd" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns clock~clkctrl 2 COMB CLKCTRL_G2 30 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 30; COMB Node = 'clock~clkctrl'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clock clock~clkctrl } "NODE_NAME" } } { "lpm_ram.vhd" "" { Text "D:/my_eda2/lpm_ram/lpm_ram.vhd" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.829 ns) + CELL(0.835 ns) 2.893 ns altsyncram:altsyncram_component\|altsyncram_03a1:auto_generated\|ram_block1a0~porta_we_reg 3 MEM M4K_X27_Y12 8 " "Info: 3: + IC(0.829 ns) + CELL(0.835 ns) = 2.893 ns; Loc. = M4K_X27_Y12; Fanout = 8; MEM Node = 'altsyncram:altsyncram_component\|altsyncram_03a1:auto_generated\|ram_block1a0~porta_we_reg'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.664 ns" { clock~clkctrl altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_we_reg } "NODE_NAME" } } { "db/altsyncram_03a1.tdf" "" { Text "D:/my_eda2/lpm_ram/db/altsyncram_03a1.tdf" 45 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.925 ns ( 66.54 % ) " "Info: Total cell delay = 1.925 ns ( 66.54 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.968 ns ( 33.46 % ) " "Info: Total interconnect delay = 0.968 ns ( 33.46 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.893 ns" { clock clock~clkctrl altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_we_reg } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.893 ns" { clock clock~combout clock~clkctrl altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_we_reg } { 0.000ns 0.000ns 0.139ns 0.829ns } { 0.000ns 1.090ns 0.000ns 0.835ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.873 ns" { clock clock~clkctrl altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[0] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.873 ns" { clock clock~combout clock~clkctrl altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[0] } { 0.000ns 0.000ns 0.139ns 0.829ns } { 0.000ns 1.090ns 0.000ns 0.815ns } "" } } { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.893 ns" { clock clock~clkctrl altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_we_reg } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.893 ns" { clock clock~combout clock~clkctrl altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_we_reg } { 0.000ns 0.000ns 0.139ns 0.829ns } { 0.000ns 1.090ns 0.000ns 0.835ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.260 ns + " "Info: + Micro clock to output delay of source is 0.260 ns" {  } { { "db/altsyncram_03a1.tdf" "" { Text "D:/my_eda2/lpm_ram/db/altsyncram_03a1.tdf" 45 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.046 ns + " "Info: + Micro setup delay of destination is 0.046 ns" {  } { { "db/altsyncram_03a1.tdf" "" { Text "D:/my_eda2/lpm_ram/db/altsyncram_03a1.tdf" 41 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "3.641 ns" { altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_we_reg altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[0] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "3.641 ns" { altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_we_reg altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[0] } { 0.000ns 0.000ns } { 0.000ns 3.641ns } "" } } { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.873 ns" { clock clock~clkctrl altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[0] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.873 ns" { clock clock~combout clock~clkctrl altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[0] } { 0.000ns 0.000ns 0.139ns 0.829ns } { 0.000ns 1.090ns 0.000ns 0.815ns } "" } } { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.893 ns" { clock clock~clkctrl altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_we_reg } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.893 ns" { clock clock~combout clock~clkctrl altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_we_reg } { 0.000ns 0.000ns 0.139ns 0.829ns } { 0.000ns 1.090ns 0.000ns 0.835ns } "" } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[0] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[0] } { 0.000ns } { 0.109ns } "" } } { "db/altsyncram_03a1.tdf" "" { Text "D:/my_eda2/lpm_ram/db/altsyncram_03a1.tdf" 41 2 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_TSU_RESULT" "altsyncram:altsyncram_component\|altsyncram_03a1:auto_generated\|ram_block1a0~porta_we_reg wren clock 5.486 ns memory " "Info: tsu for memory \"altsyncram:altsyncram_component\|altsyncram_03a1:auto_generated\|ram_block1a0~porta_we_reg\" (data pin = \"wren\", clock pin = \"clock\") is 5.486 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.333 ns + Longest pin memory " "Info: + Longest pin to memory delay is 8.333 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.934 ns) 0.934 ns wren 1 PIN PIN_67 1 " "Info: 1: + IC(0.000 ns) + CELL(0.934 ns) = 0.934 ns; Loc. = PIN_67; Fanout = 1; PIN Node = 'wren'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { wren } "NODE_NAME" } } { "lpm_ram.vhd" "" { Text "D:/my_eda2/lpm_ram/lpm_ram.vhd" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(7.015 ns) + CELL(0.384 ns) 8.333 ns altsyncram:altsyncram_component\|altsyncram_03a1:auto_generated\|ram_block1a0~porta_we_reg 2 MEM M4K_X27_Y12 8 " "Info: 2: + IC(7.015 ns) + CELL(0.384 ns) = 8.333 ns; Loc. = M4K_X27_Y12; Fanout = 8; MEM Node = 'altsyncram:altsyncram_component\|altsyncram_03a1:auto_generated\|ram_block1a0~porta_we_reg'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "7.399 ns" { wren altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_we_reg } "NODE_NAME" } } { "db/altsyncram_03a1.tdf" "" { Text "D:/my_eda2/lpm_ram/db/altsyncram_03a1.tdf" 45 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.318 ns ( 15.82 % ) " "Info: Total cell delay = 1.318 ns ( 15.82 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.015 ns ( 84.18 % ) " "Info: Total interconnect delay = 7.015 ns ( 84.18 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "8.333 ns" { wren altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_we_reg } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "8.333 ns" { wren wren~combout altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_we_reg } { 0.000ns 0.000ns 7.015ns } { 0.000ns 0.934ns 0.384ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.046 ns + " "Info: + Micro setup delay of destination is 0.046 ns" {  } { { "db/altsyncram_03a1.tdf" "" { Text "D:/my_eda2/lpm_ram/db/altsyncram_03a1.tdf" 45 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 2.893 ns - Shortest memory " "Info: - Shortest clock path from clock \"clock\" to destination memory is 2.893 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clock 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clock'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "lpm_ram.vhd" "" { Text "D:/my_eda2/lpm_ram/lpm_ram.vhd" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns clock~clkctrl 2 COMB CLKCTRL_G2 30 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 30; COMB Node = 'clock~clkctrl'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clock clock~clkctrl } "NODE_NAME" } } { "lpm_ram.vhd" "" { Text "D:/my_eda2/lpm_ram/lpm_ram.vhd" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.829 ns) + CELL(0.835 ns) 2.893 ns altsyncram:altsyncram_component\|altsyncram_03a1:auto_generated\|ram_block1a0~porta_we_reg 3 MEM M4K_X27_Y12 8 " "Info: 3: + IC(0.829 ns) + CELL(0.835 ns) = 2.893 ns; Loc. = M4K_X27_Y12; Fanout = 8; MEM Node = 'altsyncram:altsyncram_component\|altsyncram_03a1:auto_generated\|ram_block1a0~porta_we_reg'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.664 ns" { clock~clkctrl altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_we_reg } "NODE_NAME" } } { "db/altsyncram_03a1.tdf" "" { Text "D:/my_eda2/lpm_ram/db/altsyncram_03a1.tdf" 45 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.925 ns ( 66.54 % ) " "Info: Total cell delay = 1.925 ns ( 66.54 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.968 ns ( 33.46 % ) " "Info: Total interconnect delay = 0.968 ns ( 33.46 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.893 ns" { clock clock~clkctrl altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_we_reg } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.893 ns" { clock clock~combout clock~clkctrl altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_we_reg } { 0.000ns 0.000ns 0.139ns 0.829ns } { 0.000ns 1.090ns 0.000ns 0.835ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "8.333 ns" { wren altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_we_reg } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "8.333 ns" { wren wren~combout altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_we_reg } { 0.000ns 0.000ns 7.015ns } { 0.000ns 0.934ns 0.384ns } "" } } { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.893 ns" { clock clock~clkctrl altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_we_reg } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.893 ns" { clock clock~combout clock~clkctrl altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_we_reg } { 0.000ns 0.000ns 0.139ns 0.829ns } { 0.000ns 1.090ns 0.000ns 0.835ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clock q\[6\] altsyncram:altsyncram_component\|altsyncram_03a1:auto_generated\|q_a\[6\] 9.918 ns memory " "Info: tco from clock \"clock\" to destination pin \"q\[6\]\" through memory \"altsyncram:altsyncram_component\|altsyncram_03a1:auto_generated\|q_a\[6\]\" is 9.918 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 2.873 ns + Longest memory " "Info: + Longest clock path from clock \"clock\" to source memory is 2.873 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clock 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clock'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "lpm_ram.vhd" "" { Text "D:/my_eda2/lpm_ram/lpm_ram.vhd" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns clock~clkctrl 2 COMB CLKCTRL_G2 30 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 30; COMB Node = 'clock~clkctrl'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clock clock~clkctrl } "NODE_NAME" } } { "lpm_ram.vhd" "" { Text "D:/my_eda2/lpm_ram/lpm_ram.vhd" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.829 ns) + CELL(0.815 ns) 2.873 ns altsyncram:altsyncram_component\|altsyncram_03a1:auto_generated\|q_a\[6\] 3 MEM M4K_X27_Y12 1 " "Info: 3: + IC(0.829 ns) + CELL(0.815 ns) = 2.873 ns; Loc. = M4K_X27_Y12; Fanout = 1; MEM Node = 'altsyncram:altsyncram_component\|altsyncram_03a1:auto_generated\|q_a\[6\]'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.644 ns" { clock~clkctrl altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[6] } "NODE_NAME" } } { "db/altsyncram_03a1.tdf" "" { Text "D:/my_eda2/lpm_ram/db/altsyncram_03a1.tdf" 41 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.905 ns ( 66.31 % ) " "Info: Total cell delay = 1.905 ns ( 66.31 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.968 ns ( 33.69 % ) " "Info: Total interconnect delay = 0.968 ns ( 33.69 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.873 ns" { clock clock~clkctrl altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[6] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.873 ns" { clock clock~combout clock~clkctrl altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[6] } { 0.000ns 0.000ns 0.139ns 0.829ns } { 0.000ns 1.090ns 0.000ns 0.815ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.260 ns + " "Info: + Micro clock to output delay of source is 0.260 ns" {  } { { "db/altsyncram_03a1.tdf" "" { Text "D:/my_eda2/lpm_ram/db/altsyncram_03a1.tdf" 41 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.785 ns + Longest memory pin " "Info: + Longest memory to pin delay is 6.785 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.109 ns) 0.109 ns altsyncram:altsyncram_component\|altsyncram_03a1:auto_generated\|q_a\[6\] 1 MEM M4K_X27_Y12 1 " "Info: 1: + IC(0.000 ns) + CELL(0.109 ns) = 0.109 ns; Loc. = M4K_X27_Y12; Fanout = 1; MEM Node = 'altsyncram:altsyncram_component\|altsyncram_03a1:auto_generated\|q_a\[6\]'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[6] } "NODE_NAME" } } { "db/altsyncram_03a1.tdf" "" { Text "D:/my_eda2/lpm_ram/db/altsyncram_03a1.tdf" 41 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.620 ns) + CELL(3.056 ns) 6.785 ns q\[6\] 2 PIN PIN_8 0 " "Info: 2: + IC(3.620 ns) + CELL(3.056 ns) = 6.785 ns; Loc. = PIN_8; Fanout = 0; PIN Node = 'q\[6\]'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "6.676 ns" { altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[6] q[6] } "NODE_NAME" } } { "lpm_ram.vhd" "" { Text "D:/my_eda2/lpm_ram/lpm_ram.vhd" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.165 ns ( 46.65 % ) " "Info: Total cell delay = 3.165 ns ( 46.65 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.620 ns ( 53.35 % ) " "Info: Total interconnect delay = 3.620 ns ( 53.35 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "6.785 ns" { altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[6] q[6] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "6.785 ns" { altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[6] q[6] } { 0.000ns 3.620ns } { 0.109ns 3.056ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.873 ns" { clock clock~clkctrl altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[6] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.873 ns" { clock clock~combout clock~clkctrl altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[6] } { 0.000ns 0.000ns 0.139ns 0.829ns } { 0.000ns 1.090ns 0.000ns 0.815ns } "" } } { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "6.785 ns" { altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[6] q[6] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "6.785 ns" { altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[6] q[6] } { 0.000ns 3.620ns } { 0.109ns 3.056ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "altsyncram:altsyncram_component\|altsyncram_03a1:auto_generated\|ram_block1a0~porta_address_reg4 address\[4\] clock 0.260 ns memory " "Info: th for memory \"altsyncram:altsyncram_component\|altsyncram_03a1:auto_generated\|ram_block1a0~porta_address_reg4\" (data pin = \"address\[4\]\", clock pin = \"clock\") is 0.260 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 2.893 ns + Longest memory " "Info: + Longest clock path from clock \"clock\" to destination memory is 2.893 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clock 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clock'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "lpm_ram.vhd" "" { Text "D:/my_eda2/lpm_ram/lpm_ram.vhd" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns clock~clkctrl 2 COMB CLKCTRL_G2 30 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 30; COMB Node = 'clock~clkctrl'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clock clock~clkctrl } "NODE_NAME" } } { "lpm_ram.vhd" "" { Text "D:/my_eda2/lpm_ram/lpm_ram.vhd" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.829 ns) + CELL(0.835 ns) 2.893 ns altsyncram:altsyncram_component\|altsyncram_03a1:auto_generated\|ram_block1a0~porta_address_reg4 3 MEM M4K_X27_Y12 8 " "Info: 3: + IC(0.829 ns) + CELL(0.835 ns) = 2.893 ns; Loc. = M4K_X27_Y12; Fanout = 8; MEM Node = 'altsyncram:altsyncram_component\|altsyncram_03a1:auto_generated\|ram_block1a0~porta_address_reg4'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.664 ns" { clock~clkctrl altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg4 } "NODE_NAME" } } { "db/altsyncram_03a1.tdf" "" { Text "D:/my_eda2/lpm_ram/db/altsyncram_03a1.tdf" 45 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.925 ns ( 66.54 % ) " "Info: Total cell delay = 1.925 ns ( 66.54 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.968 ns ( 33.46 % ) " "Info: Total interconnect delay = 0.968 ns ( 33.46 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.893 ns" { clock clock~clkctrl altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg4 } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.893 ns" { clock clock~combout clock~clkctrl altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg4 } { 0.000ns 0.000ns 0.139ns 0.829ns } { 0.000ns 1.090ns 0.000ns 0.835ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.267 ns + " "Info: + Micro hold delay of destination is 0.267 ns" {  } { { "db/altsyncram_03a1.tdf" "" { Text "D:/my_eda2/lpm_ram/db/altsyncram_03a1.tdf" 45 2 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.900 ns - Shortest pin memory " "Info: - Shortest pin to memory delay is 2.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns address\[4\] 1 PIN PIN_89 1 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_89; Fanout = 1; PIN Node = 'address\[4\]'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { address[4] } "NODE_NAME" } } { "lpm_ram.vhd" "" { Text "D:/my_eda2/lpm_ram/lpm_ram.vhd" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.624 ns) + CELL(0.176 ns) 2.900 ns altsyncram:altsyncram_component\|altsyncram_03a1:auto_generated\|ram_block1a0~porta_address_reg4 2 MEM M4K_X27_Y12 8 " "Info: 2: + IC(1.624 ns) + CELL(0.176 ns) = 2.900 ns; Loc. = M4K_X27_Y12; Fanout = 8; MEM Node = 'altsyncram:altsyncram_component\|altsyncram_03a1:auto_generated\|ram_block1a0~porta_address_reg4'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.800 ns" { address[4] altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg4 } "NODE_NAME" } } { "db/altsyncram_03a1.tdf" "" { Text "D:/my_eda2/lpm_ram/db/altsyncram_03a1.tdf" 45 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.276 ns ( 44.00 % ) " "Info: Total cell delay = 1.276 ns ( 44.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.624 ns ( 56.00 % ) " "Info: Total interconnect delay = 1.624 ns ( 56.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.900 ns" { address[4] altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg4 } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.900 ns" { address[4] address[4]~combout altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg4 } { 0.000ns 0.000ns 1.624ns } { 0.000ns 1.100ns 0.176ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.893 ns" { clock clock~clkctrl altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg4 } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.893 ns" { clock clock~combout clock~clkctrl altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg4 } { 0.000ns 0.000ns 0.139ns 0.829ns } { 0.000ns 1.090ns 0.000ns 0.835ns } "" } } { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.900 ns" { address[4] altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg4 } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.900 ns" { address[4] address[4]~combout altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg4 } { 0.000ns 0.000ns 1.624ns } { 0.000ns 1.100ns 0.176ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}