lpm_ram.fnsim.qmsg

大量VHDL写的数字系统设计有用实例达到

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Functional Simulation Netlist Generation Quartus II " "Info: Running Quartus II Functional Simulation Netlist Generation" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.0 Build 33 02/05/2007 SJ Full Version " "Info: Version 7.0 Build 33 02/05/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Apr 23 10:18:17 2007 " "Info: Processing started: Mon Apr 23 10:18:17 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off lpm_ram -c lpm_ram --generate_functional_sim_netlist " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off lpm_ram -c lpm_ram --generate_functional_sim_netlist" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "lpm_ram.vhd 2 1 " "Warning: Using design file lpm_ram.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 lpm_ram-SYN " "Info: Found design unit 1: lpm_ram-SYN" {  } { { "lpm_ram.vhd" "" { Text "D:/my_eda2/lpm_ram/lpm_ram.vhd" 54 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 lpm_ram " "Info: Found entity 1: lpm_ram" {  } { { "lpm_ram.vhd" "" { Text "D:/my_eda2/lpm_ram/lpm_ram.vhd" 42 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "lpm_ram " "Info: Elaborating entity \"lpm_ram\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/quartus ii7.0/quartus/libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus ii7.0/quartus/libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" {  } { { "altsyncram.tdf" "" { Text "e:/altera/quartus ii7.0/quartus/libraries/megafunctions/altsyncram.tdf" 434 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram altsyncram:altsyncram_component " "Info: Elaborating entity \"altsyncram\" for hierarchy \"altsyncram:altsyncram_component\"" {  } { { "lpm_ram.vhd" "altsyncram_component" { Text "D:/my_eda2/lpm_ram/lpm_ram.vhd" 88 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "altsyncram:altsyncram_component " "Info: Elaborated megafunction instantiation \"altsyncram:altsyncram_component\"" {  } { { "lpm_ram.vhd" "" { Text "D:/my_eda2/lpm_ram/lpm_ram.vhd" 88 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_03a1.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_03a1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_03a1 " "Info: Found entity 1: altsyncram_03a1" {  } { { "db/altsyncram_03a1.tdf" "" { Text "D:/my_eda2/lpm_ram/db/altsyncram_03a1.tdf" 36 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_03a1 altsyncram:altsyncram_component\|altsyncram_03a1:auto_generated " "Info: Elaborating entity \"altsyncram_03a1\" for hierarchy \"altsyncram:altsyncram_component\|altsyncram_03a1:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "e:/altera/quartus ii7.0/quartus/libraries/megafunctions/altsyncram.tdf" 917 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Functional Simulation Netlist Generation 0 s 1  Quartus II " "Info: Quartus II Functional Simulation Netlist Generation was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "145 " "Info: Allocated 145 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon Apr 23 10:18:21 2007 " "Info: Processing ended: Mon Apr 23 10:18:21 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}