lpm_ram.tan.rpt

大量VHDL写的数字系统设计有用实例达到

; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clock           ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clock'                                                                                                                                                                                                                                                                                                                                                ;
+-------+------------------------------------------------+------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period)                           ; From                                                                                           ; To                                                                                            ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_we_reg       ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[0]                         ; clock      ; clock    ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg0 ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[0]                         ; clock      ; clock    ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg1 ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[0]                         ; clock      ; clock    ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg2 ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[0]                         ; clock      ; clock    ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg3 ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[0]                         ; clock      ; clock    ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg4 ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[0]                         ; clock      ; clock    ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_we_reg       ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[1]                         ; clock      ; clock    ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg0 ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[1]                         ; clock      ; clock    ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg1 ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[1]                         ; clock      ; clock    ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg2 ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[1]                         ; clock      ; clock    ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg3 ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[1]                         ; clock      ; clock    ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg4 ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[1]                         ; clock      ; clock    ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_we_reg       ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[2]                         ; clock      ; clock    ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg0 ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[2]                         ; clock      ; clock    ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg1 ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[2]                         ; clock      ; clock    ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg2 ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[2]                         ; clock      ; clock    ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg3 ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[2]                         ; clock      ; clock    ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg4 ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[2]                         ; clock      ; clock    ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_we_reg       ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[3]                         ; clock      ; clock    ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg0 ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[3]                         ; clock      ; clock    ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg1 ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[3]                         ; clock      ; clock    ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg2 ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[3]                         ; clock      ; clock    ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg3 ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[3]                         ; clock      ; clock    ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg4 ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[3]                         ; clock      ; clock    ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_we_reg       ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[4]                         ; clock      ; clock    ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg0 ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[4]                         ; clock      ; clock    ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg1 ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[4]                         ; clock      ; clock    ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg2 ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[4]                         ; clock      ; clock    ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg3 ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[4]                         ; clock      ; clock    ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg4 ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[4]                         ; clock      ; clock    ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_we_reg       ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[5]                         ; clock      ; clock    ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg0 ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[5]                         ; clock      ; clock    ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg1 ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[5]                         ; clock      ; clock    ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg2 ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[5]                         ; clock      ; clock    ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg3 ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[5]                         ; clock      ; clock    ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg4 ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[5]                         ; clock      ; clock    ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_we_reg       ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[6]                         ; clock      ; clock    ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg0 ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[6]                         ; clock      ; clock    ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg1 ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[6]                         ; clock      ; clock    ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg2 ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[6]                         ; clock      ; clock    ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg3 ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[6]                         ; clock      ; clock    ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg4 ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[6]                         ; clock      ; clock    ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_we_reg       ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[7]                         ; clock      ; clock    ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg0 ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[7]                         ; clock      ; clock    ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg1 ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[7]                         ; clock      ; clock    ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg2 ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[7]                         ; clock      ; clock    ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg3 ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[7]                         ; clock      ; clock    ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg4 ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[7]                         ; clock      ; clock    ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_datain_reg0  ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_memory_reg0 ; clock      ; clock    ; None                        ; None                      ; 2.931 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_datain_reg1  ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a1~porta_memory_reg0 ; clock      ; clock    ; None                        ; None                      ; 2.931 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_datain_reg2  ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a2~porta_memory_reg0 ; clock      ; clock    ; None                        ; None                      ; 2.931 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_datain_reg3  ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a3~porta_memory_reg0 ; clock      ; clock    ; None                        ; None                      ; 2.931 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_datain_reg4  ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a4~porta_memory_reg0 ; clock      ; clock    ; None                        ; None                      ; 2.931 ns                ;