lpm_ram.tan.summary

大量VHDL写的数字系统设计有用实例达到

--------------------------------------------------------------------------------------
Timing Analyzer Summary
--------------------------------------------------------------------------------------

Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 5.486 ns
From           : wren
To             : altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_we_reg
From Clock     : --
To Clock       : clock
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 9.918 ns
From           : altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[6]
To             : q[6]
From Clock     : clock
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 0.260 ns
From           : address[4]
To             : altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg4
From Clock     : --
To Clock       : clock
Failed Paths   : 0

Type           : Clock Setup: 'clock'
Slack          : N/A
Required Time  : None
Actual Time    : Restricted to 163.03 MHz ( period = 6.134 ns )
From           : altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg4
To             : altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[7]
From Clock     : clock
To Clock       : clock
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

--------------------------------------------------------------------------------------