elevator.fit.qmsg

大量VHDL写的数字系统设计有用实例达到

{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "39 unused 3.30 26 13 0 " "Info: Number of I/O pins in group: 39 (unused VREF, 3.30 VCCIO, 26 input, 13 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "Info: I/O standards used: 3.3-V LVTTL." {  } {  } 0 0 "I/O standards used: %1!s!" 0 0}  } {  } 0 0 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0}  } {  } 0 0 "Statistics of %1!s!" 0 0}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use unused 3 14 " "Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 3 total pin(s) used --  14 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use unused 0 23 " "Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  23 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use unused 1 20 " "Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  20 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use unused 0 24 " "Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  24 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0}  } {  } 0 0 "Statistics of %1!s!" 0 0}  } {  } 0 0 "I/O bank details %1!s! I/O pin placement" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "6.594 ns register register " "Info: Estimated most critical path is register to register delay of 6.594 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns k55 1 REG LAB_X17_Y11 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X17_Y11; Fanout = 4; REG Node = 'k55'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { k55 } "NODE_NAME" } } { "elevator.vhd" "" { Text "D:/my_eda2/elevator/elevator.vhd" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.511 ns) + CELL(0.370 ns) 0.881 ns en_down~1621 2 COMB LAB_X17_Y11 4 " "Info: 2: + IC(0.511 ns) + CELL(0.370 ns) = 0.881 ns; Loc. = LAB_X17_Y11; Fanout = 4; COMB Node = 'en_down~1621'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.881 ns" { k55 en_down~1621 } "NODE_NAME" } } { "elevator.vhd" "" { Text "D:/my_eda2/elevator/elevator.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.160 ns) + CELL(0.647 ns) 1.688 ns opendoor~2131 3 COMB LAB_X17_Y11 4 " "Info: 3: + IC(0.160 ns) + CELL(0.647 ns) = 1.688 ns; Loc. = LAB_X17_Y11; Fanout = 4; COMB Node = 'opendoor~2131'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.807 ns" { en_down~1621 opendoor~2131 } "NODE_NAME" } } { "elevator.vhd" "" { Text "D:/my_eda2/elevator/elevator.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.160 ns) + CELL(0.646 ns) 2.494 ns LessThan3~77 4 COMB LAB_X17_Y11 6 " "Info: 4: + IC(0.160 ns) + CELL(0.646 ns) = 2.494 ns; Loc. = LAB_X17_Y11; Fanout = 6; COMB Node = 'LessThan3~77'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.806 ns" { opendoor~2131 LessThan3~77 } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/altera/quartus ii7.0/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1473 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.935 ns) + CELL(0.624 ns) 4.053 ns en_down~1625 5 COMB LAB_X17_Y12 1 " "Info: 5: + IC(0.935 ns) + CELL(0.624 ns) = 4.053 ns; Loc. = LAB_X17_Y12; Fanout = 1; COMB Node = 'en_down~1625'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.559 ns" { LessThan3~77 en_down~1625 } "NODE_NAME" } } { "elevator.vhd" "" { Text "D:/my_eda2/elevator/elevator.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.160 ns) + CELL(0.651 ns) 4.864 ns en_down~1628 6 COMB LAB_X17_Y12 1 " "Info: 6: + IC(0.160 ns) + CELL(0.651 ns) = 4.864 ns; Loc. = LAB_X17_Y12; Fanout = 1; COMB Node = 'en_down~1628'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.811 ns" { en_down~1625 en_down~1628 } "NODE_NAME" } } { "elevator.vhd" "" { Text "D:/my_eda2/elevator/elevator.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.187 ns) + CELL(0.624 ns) 5.675 ns en_down~1630 7 COMB LAB_X17_Y12 1 " "Info: 7: + IC(0.187 ns) + CELL(0.624 ns) = 5.675 ns; Loc. = LAB_X17_Y12; Fanout = 1; COMB Node = 'en_down~1630'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.811 ns" { en_down~1628 en_down~1630 } "NODE_NAME" } } { "elevator.vhd" "" { Text "D:/my_eda2/elevator/elevator.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.160 ns) + CELL(0.651 ns) 6.486 ns en_down~1631 8 COMB LAB_X17_Y12 1 " "Info: 8: + IC(0.160 ns) + CELL(0.651 ns) = 6.486 ns; Loc. = LAB_X17_Y12; Fanout = 1; COMB Node = 'en_down~1631'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.811 ns" { en_down~1630 en_down~1631 } "NODE_NAME" } } { "elevator.vhd" "" { Text "D:/my_eda2/elevator/elevator.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 6.594 ns en_down 9 REG LAB_X17_Y12 6 " "Info: 9: + IC(0.000 ns) + CELL(0.108 ns) = 6.594 ns; Loc. = LAB_X17_Y12; Fanout = 6; REG Node = 'en_down'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { en_down~1631 en_down } "NODE_NAME" } } { "elevator.vhd" "" { Text "D:/my_eda2/elevator/elevator.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.321 ns ( 65.53 % ) " "Info: Total cell delay = 4.321 ns ( 65.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.273 ns ( 34.47 % ) " "Info: Total interconnect delay = 2.273 ns ( 34.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "6.594 ns" { k55 en_down~1621 opendoor~2131 LessThan3~77 en_down~1625 en_down~1628 en_down~1630 en_down~1631 en_down } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 2 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 2%" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "X11_Y10 X22_Y19 " "Info: The peak interconnect region extends from location X11_Y10 to location X22_Y19" {  } {  } 0 0 "The peak interconnect region extends from location %1!s! to location %2!s!" 0 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}