decoder.tan.qmsg

大量VHDL写的数字系统设计有用实例达到

{ "Info" "ITDB_TH_RESULT" "comb2_a\[0\] distance_in\[10\] clk20mhz -2.259 ns register " "Info: th for register \"comb2_a\[0\]\" (data pin = \"distance_in\[10\]\", clock pin = \"clk20mhz\") is -2.259 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk20mhz destination 2.788 ns + Longest register " "Info: + Longest clock path from clock \"clk20mhz\" to destination register is 2.788 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk20mhz 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk20mhz'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk20mhz } "NODE_NAME" } } { "decoder.vhd" "" { Text "D:/my_eda2/taxi/decoder.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns clk20mhz~clkctrl 2 COMB CLKCTRL_G2 91 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 91; COMB Node = 'clk20mhz~clkctrl'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk20mhz clk20mhz~clkctrl } "NODE_NAME" } } { "decoder.vhd" "" { Text "D:/my_eda2/taxi/decoder.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.893 ns) + CELL(0.666 ns) 2.788 ns comb2_a\[0\] 3 REG LCFF_X14_Y11_N1 5 " "Info: 3: + IC(0.893 ns) + CELL(0.666 ns) = 2.788 ns; Loc. = LCFF_X14_Y11_N1; Fanout = 5; REG Node = 'comb2_a\[0\]'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.559 ns" { clk20mhz~clkctrl comb2_a[0] } "NODE_NAME" } } { "decoder.vhd" "" { Text "D:/my_eda2/taxi/decoder.vhd" 73 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 62.98 % ) " "Info: Total cell delay = 1.756 ns ( 62.98 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.032 ns ( 37.02 % ) " "Info: Total interconnect delay = 1.032 ns ( 37.02 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.788 ns" { clk20mhz clk20mhz~clkctrl comb2_a[0] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.788 ns" { clk20mhz clk20mhz~combout clk20mhz~clkctrl comb2_a[0] } { 0.000ns 0.000ns 0.139ns 0.893ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" {  } { { "decoder.vhd" "" { Text "D:/my_eda2/taxi/decoder.vhd" 73 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.353 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.353 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns distance_in\[10\] 1 PIN PIN_89 3 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_89; Fanout = 3; PIN Node = 'distance_in\[10\]'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { distance_in[10] } "NODE_NAME" } } { "decoder.vhd" "" { Text "D:/my_eda2/taxi/decoder.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.935 ns) + CELL(0.596 ns) 3.631 ns LessThan2~212 2 COMB LCCOMB_X14_Y11_N26 1 " "Info: 2: + IC(1.935 ns) + CELL(0.596 ns) = 3.631 ns; Loc. = LCCOMB_X14_Y11_N26; Fanout = 1; COMB Node = 'LessThan2~212'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.531 ns" { distance_in[10] LessThan2~212 } "NODE_NAME" } } { "decoder.vhd" "" { Text "D:/my_eda2/taxi/decoder.vhd" 74 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 3.717 ns LessThan2~214 3 COMB LCCOMB_X14_Y11_N28 1 " "Info: 3: + IC(0.000 ns) + CELL(0.086 ns) = 3.717 ns; Loc. = LCCOMB_X14_Y11_N28; Fanout = 1; COMB Node = 'LessThan2~214'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { LessThan2~212 LessThan2~214 } "NODE_NAME" } } { "decoder.vhd" "" { Text "D:/my_eda2/taxi/decoder.vhd" 74 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.506 ns) 4.223 ns LessThan2~215 4 COMB LCCOMB_X14_Y11_N30 31 " "Info: 4: + IC(0.000 ns) + CELL(0.506 ns) = 4.223 ns; Loc. = LCCOMB_X14_Y11_N30; Fanout = 31; COMB Node = 'LessThan2~215'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.506 ns" { LessThan2~214 LessThan2~215 } "NODE_NAME" } } { "decoder.vhd" "" { Text "D:/my_eda2/taxi/decoder.vhd" 74 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.399 ns) + CELL(0.623 ns) 5.245 ns comb2_a~459 5 COMB LCCOMB_X14_Y11_N0 1 " "Info: 5: + IC(0.399 ns) + CELL(0.623 ns) = 5.245 ns; Loc. = LCCOMB_X14_Y11_N0; Fanout = 1; COMB Node = 'comb2_a~459'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.022 ns" { LessThan2~215 comb2_a~459 } "NODE_NAME" } } { "decoder.vhd" "" { Text "D:/my_eda2/taxi/decoder.vhd" 71 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 5.353 ns comb2_a\[0\] 6 REG LCFF_X14_Y11_N1 5 " "Info: 6: + IC(0.000 ns) + CELL(0.108 ns) = 5.353 ns; Loc. = LCFF_X14_Y11_N1; Fanout = 5; REG Node = 'comb2_a\[0\]'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { comb2_a~459 comb2_a[0] } "NODE_NAME" } } { "decoder.vhd" "" { Text "D:/my_eda2/taxi/decoder.vhd" 73 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.019 ns ( 56.40 % ) " "Info: Total cell delay = 3.019 ns ( 56.40 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.334 ns ( 43.60 % ) " "Info: Total interconnect delay = 2.334 ns ( 43.60 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "5.353 ns" { distance_in[10] LessThan2~212 LessThan2~214 LessThan2~215 comb2_a~459 comb2_a[0] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "5.353 ns" { distance_in[10] distance_in[10]~combout LessThan2~212 LessThan2~214 LessThan2~215 comb2_a~459 comb2_a[0] } { 0.000ns 0.000ns 1.935ns 0.000ns 0.000ns 0.399ns 0.000ns } { 0.000ns 1.100ns 0.596ns 0.086ns 0.506ns 0.623ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.788 ns" { clk20mhz clk20mhz~clkctrl comb2_a[0] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.788 ns" { clk20mhz clk20mhz~combout clk20mhz~clkctrl comb2_a[0] } { 0.000ns 0.000ns 0.139ns 0.893ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "5.353 ns" { distance_in[10] LessThan2~212 LessThan2~214 LessThan2~215 comb2_a~459 comb2_a[0] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "5.353 ns" { distance_in[10] distance_in[10]~combout LessThan2~212 LessThan2~214 LessThan2~215 comb2_a~459 comb2_a[0] } { 0.000ns 0.000ns 1.935ns 0.000ns 0.000ns 0.399ns 0.000ns } { 0.000ns 1.100ns 0.596ns 0.086ns 0.506ns 0.623ns 0.108ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "102 " "Info: Allocated 102 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Apr 19 15:40:51 2007 " "Info: Processing ended: Thu Apr 19 15:40:51 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}