phase_shift_sin.sim.rpt
来自「实现低频率的移相信号发生器,才用DDS技术直接的合成」· RPT 代码 · 共 300 行 · 第 1/5 页
RPT
300 行
The following table displays output ports that toggle between 1 and 0 during simulation.
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; Complete 1/0-Value Coverage ;
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; Node Name ; Output Port Name ; Output Port Type ;
+------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------+------------------+
; |phase_shift_sin|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_66u:auto_generated|altsyncram_4r92:altsyncram1|q_a[0] ; |phase_shift_sin|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_66u:auto_generated|altsyncram_4r92:altsyncram1|q_a[0] ; portadataout0 ;
; |phase_shift_sin|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_66u:auto_generated|altsyncram_4r92:altsyncram1|q_a[0] ; |phase_shift_sin|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_66u:auto_generated|altsyncram_4r92:altsyncram1|q_a[1] ; portadataout1 ;
; |phase_shift_sin|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_66u:auto_generated|altsyncram_4r92:altsyncram1|q_a[0] ; |phase_shift_sin|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_66u:auto_generated|altsyncram_4r92:altsyncram1|q_a[2] ; portadataout2 ;
; |phase_shift_sin|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_66u:auto_generated|altsyncram_4r92:altsyncram1|q_a[0] ; |phase_shift_sin|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_66u:auto_generated|altsyncram_4r92:altsyncram1|q_a[3] ; portadataout3 ;
; |phase_shift_sin|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_66u:auto_generated|altsyncram_4r92:altsyncram1|q_a[0] ; |phase_shift_sin|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_66u:auto_generated|altsyncram_4r92:altsyncram1|q_a[4] ; portadataout4 ;
; |phase_shift_sin|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_66u:auto_generated|altsyncram_4r92:altsyncram1|q_a[0] ; |phase_shift_sin|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_66u:auto_generated|altsyncram_4r92:altsyncram1|q_a[5] ; portadataout5 ;
; |phase_shift_sin|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_66u:auto_generated|altsyncram_4r92:altsyncram1|q_a[0] ; |phase_shift_sin|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_66u:auto_generated|altsyncram_4r92:altsyncram1|q_a[6] ; portadataout6 ;
; |phase_shift_sin|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_66u:auto_generated|altsyncram_4r92:altsyncram1|q_a[0] ; |phase_shift_sin|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_66u:auto_generated|altsyncram_4r92:altsyncram1|q_a[7] ; portadataout7 ;
; |phase_shift_sin|sin_rom:u4|altsyncram:altsyncram_component|altsyncram_66u:auto_generated|altsyncram_4r92:altsyncram1|q_a[0] ; |phase_shift_sin|sin_rom:u4|altsyncram:altsyncram_component|altsyncram_66u:auto_generated|altsyncram_4r92:altsyncram1|q_a[0] ; portadataout0 ;
; |phase_shift_sin|sin_rom:u4|altsyncram:altsyncram_component|altsyncram_66u:auto_generated|altsyncram_4r92:altsyncram1|q_a[0] ; |phase_shift_sin|sin_rom:u4|altsyncram:altsyncram_component|altsyncram_66u:auto_generated|altsyncram_4r92:altsyncram1|q_a[1] ; portadataout1 ;
; |phase_shift_sin|sin_rom:u4|altsyncram:altsyncram_component|altsyncram_66u:auto_generated|altsyncram_4r92:altsyncram1|q_a[0] ; |phase_shift_sin|sin_rom:u4|altsyncram:altsyncram_component|altsyncram_66u:auto_generated|altsyncram_4r92:altsyncram1|q_a[2] ; portadataout2 ;
; |phase_shift_sin|sin_rom:u4|altsyncram:altsyncram_component|altsyncram_66u:auto_generated|altsyncram_4r92:altsyncram1|q_a[0] ; |phase_shift_sin|sin_rom:u4|altsyncram:altsyncram_component|altsyncram_66u:auto_generated|altsyncram_4r92:altsyncram1|q_a[3] ; portadataout3 ;
; |phase_shift_sin|sin_rom:u4|altsyncram:altsyncram_component|altsyncram_66u:auto_generated|altsyncram_4r92:altsyncram1|q_a[0] ; |phase_shift_sin|sin_rom:u4|altsyncram:altsyncram_component|altsyncram_66u:auto_generated|altsyncram_4r92:altsyncram1|q_a[4] ; portadataout4 ;
; |phase_shift_sin|sin_rom:u4|altsyncram:altsyncram_component|altsyncram_66u:auto_generated|altsyncram_4r92:altsyncram1|q_a[0] ; |phase_shift_sin|sin_rom:u4|altsyncram:altsyncram_component|altsyncram_66u:auto_generated|altsyncram_4r92:altsyncram1|q_a[5] ; portadataout5 ;
; |phase_shift_sin|sin_rom:u4|altsyncram:altsyncram_component|altsyncram_66u:auto_generated|altsyncram_4r92:altsyncram1|q_a[0] ; |phase_shift_sin|sin_rom:u4|altsyncram:altsyncram_component|altsyncram_66u:auto_generated|altsyncram_4r92:altsyncram1|q_a[6] ; portadataout6 ;
; |phase_shift_sin|sin_rom:u4|altsyncram:altsyncram_component|altsyncram_66u:auto_generated|altsyncram_4r92:altsyncram1|q_a[0] ; |phase_shift_sin|sin_rom:u4|altsyncram:altsyncram_component|altsyncram_66u:auto_generated|altsyncram_4r92:altsyncram1|q_a[7] ; portadataout7 ;
; |phase_shift_sin|fword2[24] ; |phase_shift_sin|fword2[24] ; regout ;
; |phase_shift_sin|fword2[24] ; |phase_shift_sin|fword2[24]~85 ; cout0 ;
; |phase_shift_sin|fword2[24] ; |phase_shift_sin|fword2[24]~85COUT1_136 ; cout1 ;
; |phase_shift_sin|fword2[25] ; |phase_shift_sin|fword2[25] ; regout ;
; |phase_shift_sin|fword2[25] ; |phase_shift_sin|fword2[25]~89 ; cout ;
; |phase_shift_sin|fword2[26] ; |phase_shift_sin|fword2[26] ; regout ;
; |phase_shift_sin|fword2[26] ; |phase_shift_sin|fword2[26]~93COUT1_137 ; cout1 ;
; |phase_shift_sin|fword2[27] ; |phase_shift_sin|fword2[27] ; regout ;
; |phase_shift_sin|fword2[27] ; |phase_shift_sin|fword2[27]~97COUT1_138 ; cout1 ;
; |phase_shift_sin|fword2[28] ; |phase_shift_sin|fword2[28] ; regout ;
; |phase_shift_sin|fword2[28] ; |phase_shift_sin|fword2[28]~101 ; cout0 ;
; |phase_shift_sin|fword2[28] ; |phase_shift_sin|fword2[28]~101COUT1_139 ; cout1 ;
; |phase_shift_sin|fword2[29] ; |phase_shift_sin|fword2[29] ; regout ;
; |phase_shift_sin|fword2[29] ; |phase_shift_sin|fword2[29]~105 ; cout0 ;
; |phase_shift_sin|fword2[29] ; |phase_shift_sin|fword2[29]~105COUT1_140 ; cout1 ;
; |phase_shift_sin|fword2[30] ; |phase_shift_sin|fword2[30] ; regout ;
; |phase_shift_sin|fword2[30] ; |phase_shift_sin|fword2[30]~109 ; cout ;
; |phase_shift_sin|fword2[31] ; |phase_shift_sin|fword2[31] ; regout ;
; |phase_shift_sin|pword2[0] ; |phase_shift_sin|pword2[0] ; regout ;
; |phase_shift_sin|pword2[1] ; |phase_shift_sin|pword2[1] ; regout ;
; |phase_shift_sin|pword2[1] ; |phase_shift_sin|pword2[1]~61 ; cout0 ;
; |phase_shift_sin|pword2[1] ; |phase_shift_sin|pword2[1]~61COUT1_90 ; cout1 ;
; |phase_shift_sin|pword2[2] ; |phase_shift_sin|pword2[2] ; regout ;
; |phase_shift_sin|pword2[2] ; |phase_shift_sin|pword2[2]~65 ; cout0 ;
; |phase_shift_sin|pword2[2] ; |phase_shift_sin|pword2[2]~65COUT1_91 ; cout1 ;
; |phase_shift_sin|pword2[3] ; |phase_shift_sin|pword2[3] ; regout ;
; |phase_shift_sin|pword2[3] ; |phase_shift_sin|pword2[3]~69 ; cout0 ;
; |phase_shift_sin|pword2[3] ; |phase_shift_sin|pword2[3]~69COUT1 ; cout1 ;
; |phase_shift_sin|pword2[4] ; |phase_shift_sin|pword2[4] ; regout ;
; |phase_shift_sin|pword2[4] ; |phase_shift_sin|pword2[4]~73 ; cout ;
; |phase_shift_sin|pword2[5] ; |phase_shift_sin|pword2[5] ; regout ;
; |phase_shift_sin|pword2[5] ; |phase_shift_sin|pword2[5]~77 ; cout0 ;
; |phase_shift_sin|pword2[6] ; |phase_shift_sin|pword2[6] ; regout ;
; |phase_shift_sin|pword2[6] ; |phase_shift_sin|pword2[6]~81 ; cout0 ;
; |phase_shift_sin|pword2[7] ; |phase_shift_sin|pword2[7] ; regout ;
; |phase_shift_sin|fword2[23] ; |phase_shift_sin|fword2[23]~117 ; cout0 ;
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