hdpdeps.ref

用VHDL语言开发的一个16位的具有5级流水线的CPU设计

V3 23
FL F:/project/CPU16/cache.vhd 2008/05/07.01:19:00 J.30
EN work/cache 1210094350 FL F:/project/CPU16/cache.vhd PB ieee/std_logic_1164 1163575071 \
      PB ieee/std_logic_arith 1163575072 PB ieee/STD_LOGIC_UNSIGNED 1163575073
AR work/cache/Behavioral 1210094351 \
      FL F:/project/CPU16/cache.vhd EN work/cache 1210094350 CP memory CP mem1
FL F:/project/CPU16/four.vhd 2008/05/05.21:39:23 J.30
EN work/four 1210094352 FL F:/project/CPU16/four.vhd PB ieee/std_logic_1164 1163575071 \
      PB ieee/std_logic_arith 1163575072 PB ieee/STD_LOGIC_UNSIGNED 1163575073
AR work/four/Behavioral 1210094353 \
      FL F:/project/CPU16/four.vhd EN work/four 1210094352
FL F:/project/CPU16/kernel.vhd 2008/05/05.10:12:31 J.30
EN work/kernel 1210094348 FL F:/project/CPU16/kernel.vhd PB ieee/std_logic_1164 1163575071 \
      PB ieee/std_logic_arith 1163575072 PB ieee/STD_LOGIC_UNSIGNED 1163575073
AR work/kernel/Behavioral 1210094349 \
      FL F:/project/CPU16/kernel.vhd EN work/kernel 1210094348
FL F:/project/CPU16/mem1.vhd 2008/05/05.21:16:46 J.30
EN work/mem1 1210094346 FL F:/project/CPU16/mem1.vhd PB ieee/std_logic_1164 1163575071
AR work/mem1/mem1_a 1210094347 \
      FL F:/project/CPU16/mem1.vhd EN work/mem1 1210094346
FL F:/project/CPU16/memory.vhd 2008/05/05.20:59:54 J.30
EN work/memory 1210094344 FL F:/project/CPU16/memory.vhd PB ieee/std_logic_1164 1163575071
AR work/memory/memory_a 1210094345 \
      FL F:/project/CPU16/memory.vhd EN work/memory 1210094344
FL F:/project/CPU16/top.vhd 2008/05/05.21:40:57 J.30
EN work/top 1210094354 FL F:/project/CPU16/top.vhd PB ieee/std_logic_1164 1163575071 \
      PB ieee/std_logic_arith 1163575072 PB ieee/STD_LOGIC_UNSIGNED 1163575073
AR work/top/Behavioral 1210094355 \
      FL F:/project/CPU16/top.vhd EN work/top 1210094354 CP kernel CP cache CP four