hdllib.ref

用VHDL语言开发的一个16位的具有5级流水线的CPU设计

EN four NULL F:/project/CPU16/four.vhd sub00/vhpl06 1210094352
AR four behavioral F:/project/CPU16/four.vhd sub00/vhpl07 1210094353
EN cache NULL F:/project/CPU16/cache.vhd sub00/vhpl04 1210094350
EN top NULL F:/project/CPU16/top.vhd sub00/vhpl02 1210094354
EN memory NULL F:/project/CPU16/memory.vhd sub00/vhpl08 1210094344
AR top behavioral F:/project/CPU16/top.vhd sub00/vhpl03 1210094355
AR memory memory_a F:/project/CPU16/memory.vhd sub00/vhpl09 1210094345
EN mem1 NULL F:/project/CPU16/mem1.vhd sub00/vhpl10 1210094346
EN kernel NULL F:/project/CPU16/kernel.vhd sub00/vhpl00 1210094348
AR cache behavioral F:/project/CPU16/cache.vhd sub00/vhpl05 1210094351
AR kernel behavioral F:/project/CPU16/kernel.vhd sub00/vhpl01 1210094349
AR mem1 mem1_a F:/project/CPU16/mem1.vhd sub00/vhpl11 1210094347