top_usage.xml

用VHDL语言开发的一个16位的具有5级流水线的CPU设计

<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
     by the Xilinx ISE software.  Any direct editing or
     changes made to this file may result in unpredictable
     behavior or data corruption.  It is strongly advised that
     users do not edit the contents of this file. -->
<DeviceUsageSummary rev="1">
<DesignStatistics TimeStamp="Wed May 07 00:26:57 2008"><group name="MiscellaneousStatistics">
<item name="AVG_LUT_FAN_IN" rev="1">
<attrib name="value" value="3.250000"/></item>
<item name="AVG_SIG_FANOUT" rev="1">
<attrib name="value" value="8.000000"/></item>
<item name="LUT" rev="1">
<attrib name="value" value="4"/></item>
<item name="MAX_SIG_FANOUT" rev="1">
<attrib name="value" value="16"/></item>
<item name="PK_NUM_4_INPUT_LUTS" rev="1">
<attrib name="value" value="4"/></item>
<item name="PK_NUM_BONDED_IOBS" rev="1">
<attrib name="value" value="63"/></item>
<item name="PK_NUM_EQUIV_GATES" rev="1">
<attrib name="value" value="32"/></item>
<item name="PK_NUM_JTAG_GATES" rev="1">
<attrib name="value" value="64"/></item>
<item name="PK_NUM_LUTLESS_SLICE_FFS" rev="1">
<attrib name="value" value="1"/></item>
<item name="PK_NUM_SLICES" rev="1">
<attrib name="value" value="3"/></item>
<item name="PK_NUM_SLICE_FFS" rev="1">
<attrib name="value" value="1"/></item>
<item name="PK_NUM_TOTAL_LUTLESS_REGISTER" rev="1">
<attrib name="value" value="1"/></item>
<item name="PK_NUM_XVK_GCLKIOBS" rev="1">
<attrib name="value" value="1"/></item>
<item name="PK_NUM_XVK_GCLKS" rev="1">
<attrib name="value" value="1"/></item>
<item name="SINGLE_LOAD_SIG" rev="1">
<attrib name="value" value="2"/></item>
<item name="Xilinx Core blkmemsp_v6_2, Coregen 9.1i" rev="1">
<attrib name="value" value="5"/></item>
</group>
</DesignStatistics>
<CmdHistory>
</CmdHistory>
</DeviceUsageSummary>