📄 adc.tan.qmsg

📁 用verilog编程实现的基于FPGA的AD数据采集程序
💻 QMSG
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{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "ad_sts register register adc_4:inst11\|f_r adc_4:inst11\|f_r 333.33 MHz Internal " "Info: Clock \"ad_sts\" Internal fmax is restricted to 333.33 MHz between source register \"adc_4:inst11\|f_r\" and destination register \"adc_4:inst11\|f_r\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.5 ns 1.5 ns 3.0 ns " "Info: fmax restricted to Clock High delay (1.5 ns) plus Clock Low delay (1.5 ns) : restricted to 3.0 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.500 ns + Longest register register " "Info: + Longest register to register delay is 0.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns adc_4:inst11\|f_r 1 REG LC3_H2 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3_H2; Fanout = 4; REG Node = 'adc_4:inst11\|f_r'" {  } { { "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" "" { Report "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc.quartus_db" { Floorplan "D:/altera/qdesigns50/zdx/ADC模块_r/adc/" "" "" { adc_4:inst11|f_r } "NODE_NAME" } "" } } { "../adc_4/adc_4.v" "" { Text "D:/altera/qdesigns50/zdx/ADC模块_r/adc_4/adc_4.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.100 ns) 0.500 ns adc_4:inst11\|f_r 2 REG LC3_H2 4 " "Info: 2: + IC(0.400 ns) + CELL(0.100 ns) = 0.500 ns; Loc. = LC3_H2; Fanout = 4; REG Node = 'adc_4:inst11\|f_r'" {  } { { "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" "" { Report "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc.quartus_db" { Floorplan "D:/altera/qdesigns50/zdx/ADC模块_r/adc/" "" "0.500 ns" { adc_4:inst11|f_r adc_4:inst11|f_r } "NODE_NAME" } "" } } { "../adc_4/adc_4.v" "" { Text "D:/altera/qdesigns50/zdx/ADC模块_r/adc_4/adc_4.v" 3 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.100 ns 20.00 % " "Info: Total cell delay = 0.100 ns ( 20.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns 80.00 % " "Info: Total interconnect delay = 0.400 ns ( 80.00 % )" {  } {  } 0}  } { { "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" "" { Report "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc.quartus_db" { Floorplan "D:/altera/qdesigns50/zdx/ADC模块_r/adc/" "" "0.500 ns" { adc_4:inst11|f_r adc_4:inst11|f_r } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "0.500 ns" { adc_4:inst11|f_r adc_4:inst11|f_r } { 0.000ns 0.400ns } { 0.000ns 0.100ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "ad_sts destination 3.500 ns + Shortest register " "Info: + Shortest clock path from clock \"ad_sts\" to destination register is 3.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns ad_sts 1 CLK PIN_103 13 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_103; Fanout = 13; CLK Node = 'ad_sts'" {  } { { "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" "" { Report "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc.quartus_db" { Floorplan "D:/altera/qdesigns50/zdx/ADC模块_r/adc/" "" "" { ad_sts } "NODE_NAME" } "" } } { "../adc_4/adc.bdf" "" { Schematic "D:/altera/qdesigns50/zdx/ADC模块_r/adc_4/adc.bdf" { { 32 -24 144 48 "ad_sts" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.500 ns) + CELL(0.000 ns) 3.500 ns adc_4:inst11\|f_r 2 REG LC3_H2 4 " "Info: 2: + IC(1.500 ns) + CELL(0.000 ns) = 3.500 ns; Loc. = LC3_H2; Fanout = 4; REG Node = 'adc_4:inst11\|f_r'" {  } { { "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" "" { Report "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc.quartus_db" { Floorplan "D:/altera/qdesigns50/zdx/ADC模块_r/adc/" "" "1.500 ns" { ad_sts adc_4:inst11|f_r } "NODE_NAME" } "" } } { "../adc_4/adc_4.v" "" { Text "D:/altera/qdesigns50/zdx/ADC模块_r/adc_4/adc_4.v" 3 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns 57.14 % " "Info: Total cell delay = 2.000 ns ( 57.14 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.500 ns 42.86 % " "Info: Total interconnect delay = 1.500 ns ( 42.86 % )" {  } {  } 0}  } { { "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" "" { Report "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc.quartus_db" { Floorplan "D:/altera/qdesigns50/zdx/ADC模块_r/adc/" "" "3.500 ns" { ad_sts adc_4:inst11|f_r } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.500 ns" { ad_sts ad_sts~out adc_4:inst11|f_r } { 0.000ns 0.000ns 1.500ns } { 0.000ns 2.000ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "ad_sts source 3.500 ns - Longest register " "Info: - Longest clock path from clock \"ad_sts\" to source register is 3.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns ad_sts 1 CLK PIN_103 13 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_103; Fanout = 13; CLK Node = 'ad_sts'" {  } { { "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" "" { Report "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc.quartus_db" { Floorplan "D:/altera/qdesigns50/zdx/ADC模块_r/adc/" "" "" { ad_sts } "NODE_NAME" } "" } } { "../adc_4/adc.bdf" "" { Schematic "D:/altera/qdesigns50/zdx/ADC模块_r/adc_4/adc.bdf" { { 32 -24 144 48 "ad_sts" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.500 ns) + CELL(0.000 ns) 3.500 ns adc_4:inst11\|f_r 2 REG LC3_H2 4 " "Info: 2: + IC(1.500 ns) + CELL(0.000 ns) = 3.500 ns; Loc. = LC3_H2; Fanout = 4; REG Node = 'adc_4:inst11\|f_r'" {  } { { "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" "" { Report "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc.quartus_db" { Floorplan "D:/altera/qdesigns50/zdx/ADC模块_r/adc/" "" "1.500 ns" { ad_sts adc_4:inst11|f_r } "NODE_NAME" } "" } } { "../adc_4/adc_4.v" "" { Text "D:/altera/qdesigns50/zdx/ADC模块_r/adc_4/adc_4.v" 3 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns 57.14 % " "Info: Total cell delay = 2.000 ns ( 57.14 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.500 ns 42.86 % " "Info: Total interconnect delay = 1.500 ns ( 42.86 % )" {  } {  } 0}  } { { "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" "" { Report "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc.quartus_db" { Floorplan "D:/altera/qdesigns50/zdx/ADC模块_r/adc/" "" "3.500 ns" { ad_sts adc_4:inst11|f_r } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.500 ns" { ad_sts ad_sts~out adc_4:inst11|f_r } { 0.000ns 0.000ns 1.500ns } { 0.000ns 2.000ns 0.000ns } } }  } 0}  } { { "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" "" { Report "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc.quartus_db" { Floorplan "D:/altera/qdesigns50/zdx/ADC模块_r/adc/" "" "3.500 ns" { ad_sts adc_4:inst11|f_r } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.500 ns" { ad_sts ad_sts~out adc_4:inst11|f_r } { 0.000ns 0.000ns 1.500ns } { 0.000ns 2.000ns 0.000ns } } } { "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" "" { Report "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc.quartus_db" { Floorplan "D:/altera/qdesigns50/zdx/ADC模块_r/adc/" "" "3.500 ns" { ad_sts adc_4:inst11|f_r } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.500 ns" { ad_sts ad_sts~out adc_4:inst11|f_r } { 0.000ns 0.000ns 1.500ns } { 0.000ns 2.000ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.600 ns + " "Info: + Micro clock to output delay of source is 0.600 ns" {  } { { "../adc_4/adc_4.v" "" { Text "D:/altera/qdesigns50/zdx/ADC模块_r/adc_4/adc_4.v" 3 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.400 ns + " "Info: + Micro setup delay of destination is 0.400 ns" {  } { { "../adc_4/adc_4.v" "" { Text "D:/altera/qdesigns50/zdx/ADC模块_r/adc_4/adc_4.v" 3 -1 0 } }  } 0}  } { { "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" "" { Report "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc.quartus_db" { Floorplan "D:/altera/qdesigns50/zdx/ADC模块_r/adc/" "" "0.500 ns" { adc_4:inst11|f_r adc_4:inst11|f_r } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "0.500 ns" { adc_4:inst11|f_r adc_4:inst11|f_r } { 0.000ns 0.400ns } { 0.000ns 0.100ns } } } { "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" "" { Report "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc.quartus_db" { Floorplan "D:/altera/qdesigns50/zdx/ADC模块_r/adc/" "" "3.500 ns" { ad_sts adc_4:inst11|f_r } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.500 ns" { ad_sts ad_sts~out adc_4:inst11|f_r } { 0.000ns 0.000ns 1.500ns } { 0.000ns 2.000ns 0.000ns } } } { "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" "" { Report "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc.quartus_db" { Floorplan "D:/altera/qdesigns50/zdx/ADC模块_r/adc/" "" "3.500 ns" { ad_sts adc_4:inst11|f_r } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.500 ns" { ad_sts ad_sts~out adc_4:inst11|f_r } { 0.000ns 0.000ns 1.500ns } { 0.000ns 2.000ns 0.000ns } } }  } 0}  } { { "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" "" { Report "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc.quartus_db" { Floorplan "D:/altera/qdesigns50/zdx/ADC模块_r/adc/" "" "" { adc_4:inst11|f_r } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { adc_4:inst11|f_r } {  } {  } } } { "../adc_4/adc_4.v" "" { Text "D:/altera/qdesigns50/zdx/ADC模块_r/adc_4/adc_4.v" 3 -1 0 } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "adc_3:inst10\|data_out\[2\] data_in\[2\] ad_sts 0.900 ns register " "Info: tsu for register \"adc_3:inst10\|data_out\[2\]\" (data pin = \"data_in\[2\]\", clock pin = \"ad_sts\") is 0.900 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.000 ns + Longest pin register " "Info: + Longest pin to register delay is 4.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns data_in\[2\] 1 PIN PIN_92 1 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_92; Fanout = 1; PIN Node = 'data_in\[2\]'" {  } { { "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" "" { Report "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc.quartus_db" { Floorplan "D:/altera/qdesigns50/zdx/ADC模块_r/adc/" "" "" { data_in[2] } "NODE_NAME" } "" } } { "../adc_4/adc.bdf" "" { Schematic "D:/altera/qdesigns50/zdx/ADC模块_r/adc_4/adc.bdf" { { 464 624 792 480 "data_in\[11..0\]" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.900 ns) + CELL(0.100 ns) 4.000 ns adc_3:inst10\|data_out\[2\] 2 REG LC5_H2 1 " "Info: 2: + IC(1.900 ns) + CELL(0.100 ns) = 4.000 ns; Loc. = LC5_H2; Fanout = 1; REG Node = 'adc_3:inst10\|data_out\[2\]'" {  } { { "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" "" { Report "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc.quartus_db" { Floorplan "D:/altera/qdesigns50/zdx/ADC模块_r/adc/" "" "2.000 ns" { data_in[2] adc_3:inst10|data_out[2] } "NODE_NAME" } "" } } { "../adc_3/adc_3.v" "" { Text "D:/altera/qdesigns50/zdx/ADC模块_r/adc_3/adc_3.v" 5 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.100 ns 52.50 % " "Info: Total cell delay = 2.100 ns ( 52.50 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.900 ns 47.50 % " "Info: Total interconnect delay = 1.900 ns ( 47.50 % )" {  } {  } 0}  } { { "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" "" { Report "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc.quartus_db" { Floorplan "D:/altera/qdesigns50/zdx/ADC模块_r/adc/" "" "4.000 ns" { data_in[2] adc_3:inst10|data_out[2] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "4.000 ns" { data_in[2] data_in[2]~out adc_3:inst10|data_out[2] } { 0.000ns 0.000ns 1.900ns } { 0.000ns 2.000ns 0.100ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.400 ns + " "Info: + Micro setup delay of destination is 0.400 ns" {  } { { "../adc_3/adc_3.v" "" { Text "D:/altera/qdesigns50/zdx/ADC模块_r/adc_3/adc_3.v" 5 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "ad_sts destination 3.500 ns - Shortest register " "Info: - Shortest clock path from clock \"ad_sts\" to destination register is 3.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns ad_sts 1 CLK PIN_103 13 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_103; Fanout = 13; CLK Node = 'ad_sts'" {  } { { "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" "" { Report "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc.quartus_db" { Floorplan "D:/altera/qdesigns50/zdx/ADC模块_r/adc/" "" "" { ad_sts } "NODE_NAME" } "" } } { "../adc_4/adc.bdf" "" { Schematic "D:/altera/qdesigns50/zdx/ADC模块_r/adc_4/adc.bdf" { { 32 -24 144 48 "ad_sts" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.500 ns) + CELL(0.000 ns) 3.500 ns adc_3:inst10\|data_out\[2\] 2 REG LC5_H2 1 " "Info: 2: + IC(1.500 ns) + CELL(0.000 ns) = 3.500 ns; Loc. = LC5_H2; Fanout = 1; REG Node = 'adc_3:inst10\|data_out\[2\]'" {  } { { "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" "" { Report "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc.quartus_db" { Floorplan "D:/altera/qdesigns50/zdx/ADC模块_r/adc/" "" "1.500 ns" { ad_sts adc_3:inst10|data_out[2] } "NODE_NAME" } "" } } { "../adc_3/adc_3.v" "" { Text "D:/altera/qdesigns50/zdx/ADC模块_r/adc_3/adc_3.v" 5 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns 57.14 % " "Info: Total cell delay = 2.000 ns ( 57.14 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.500 ns 42.86 % " "Info: Total interconnect delay = 1.500 ns ( 42.86 % )" {  } {  } 0}  } { { "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" "" { Report "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc.quartus_db" { Floorplan "D:/altera/qdesigns50/zdx/ADC模块_r/adc/" "" "3.500 ns" { ad_sts adc_3:inst10|data_out[2] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.500 ns" { ad_sts ad_sts~out adc_3:inst10|data_out[2] } { 0.000ns 0.000ns 1.500ns } { 0.000ns 2.000ns 0.000ns } } }  } 0}  } { { "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" "" { Report "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc.quartus_db" { Floorplan "D:/altera/qdesigns50/zdx/ADC模块_r/adc/" "" "4.000 ns" { data_in[2] adc_3:inst10|data_out[2] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "4.000 ns" { data_in[2] data_in[2]~out adc_3:inst10|data_out[2] } { 0.000ns 0.000ns 1.900ns } { 0.000ns 2.000ns 0.100ns } } } { "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" "" { Report "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc.quartus_db" { Floorplan "D:/altera/qdesigns50/zdx/ADC模块_r/adc/" "" "3.500 ns" { ad_sts adc_3:inst10|data_out[2] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.500 ns" { ad_sts ad_sts~out adc_3:inst10|data_out[2] } { 0.000ns 0.000ns 1.500ns } { 0.000ns 2.000ns 0.000ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "ad_sts data_out1\[0\] adc_3:inst10\|data_out\[0\] 11.400 ns register " "Info: tco from clock \"ad_sts\" to destination pin \"data_out1\[0\]\" through register \"adc_3:inst10\|data_out\[0\]\" is 11.400 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "ad_sts source 4.300 ns + Longest register " "Info: + Longest clock path from clock \"ad_sts\" to source register is 4.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns ad_sts 1 CLK PIN_103 13 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_103; Fanout = 13; CLK Node = 'ad_sts'" {  } { { "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" "" { Report "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc.quartus_db" { Floorplan "D:/altera/qdesigns50/zdx/ADC模块_r/adc/" "" "" { ad_sts } "NODE_NAME" } "" } } { "../adc_4/adc.bdf" "" { Schematic "D:/altera/qdesigns50/zdx/ADC模块_r/adc_4/adc.bdf" { { 32 -24 144 48 "ad_sts" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.300 ns) + CELL(0.000 ns) 4.300 ns adc_3:inst10\|data_out\[0\] 2 REG LC7_D12 1 " "Info: 2: + IC(2.300 ns) + CELL(0.000 ns) = 4.300 ns; Loc. = LC7_D12; Fanout = 1; REG Node = 'adc_3:inst10\|data_out\[0\]'" {  } { { "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" "" { Report "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc.quartus_db" { Floorplan "D:/altera/qdesigns50/zdx/ADC模块_r/adc/" "" "2.300 ns" { ad_sts adc_3:inst10|data_out[0] } "NODE_NAME" } "" } } { "../adc_3/adc_3.v" "" { Text "D:/altera/qdesigns50/zdx/ADC模块_r/adc_3/adc_3.v" 5 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns 46.51 % " "Info: Total cell delay = 2.000 ns ( 46.51 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.300 ns 53.49 % " "Info: Total interconnect delay = 2.300 ns ( 53.49 % )" {  } {  } 0}  } { { "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" "" { Report "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc.quartus_db" { Floorplan "D:/altera/qdesigns50/zdx/ADC模块_r/adc/" "" "4.300 ns" { ad_sts adc_3:inst10|data_out[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "4.300 ns" { ad_sts ad_sts~out adc_3:inst10|data_out[0] } { 0.000ns 0.000ns 2.300ns } { 0.000ns 2.000ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.600 ns + " "Info: + Micro clock to output delay of source is 0.600 ns" {  } { { "../adc_3/adc_3.v" "" { Text "D:/altera/qdesigns50/zdx/ADC模块_r/adc_3/adc_3.v" 5 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.500 ns + Longest register pin " "Info: + Longest register to pin delay is 6.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns adc_3:inst10\|data_out\[0\] 1 REG LC7_D12 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC7_D12; Fanout = 1; REG Node = 'adc_3:inst10\|data_out\[0\]'" {  } { { "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" "" { Report "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc.quartus_db" { Floorplan "D:/altera/qdesigns50/zdx/ADC模块_r/adc/" "" "" { adc_3:inst10|data_out[0] } "NODE_NAME" } "" } } { "../adc_3/adc_3.v" "" { Text "D:/altera/qdesigns50/zdx/ADC模块_r/adc_3/adc_3.v" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.300 ns) + CELL(4.200 ns) 6.500 ns data_out1\[0\] 2 PIN PIN_47 0 " "Info: 2: + IC(2.300 ns) + CELL(4.200 ns) = 6.500 ns; Loc. = PIN_47; Fanout = 0; PIN Node = 'data_out1\[0\]'" {  } { { "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" "" { Report "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc.quartus_db" { Floorplan "D:/altera/qdesigns50/zdx/ADC模块_r/adc/" "" "6.500 ns" { adc_3:inst10|data_out[0] data_out1[0] } "NODE_NAME" } "" } } { "../adc_4/adc.bdf" "" { Schematic "D:/altera/qdesigns50/zdx/ADC模块_r/adc_4/adc.bdf" { { -240 1072 1248 -224 "data_out1\[11..0\]" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.200 ns 64.62 % " "Info: Total cell delay = 4.200 ns ( 64.62 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.300 ns 35.38 % " "Info: Total interconnect delay = 2.300 ns ( 35.38 % )" {  } {  } 0}  } { { "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" "" { Report "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc.quartus_db" { Floorplan "D:/altera/qdesigns50/zdx/ADC模块_r/adc/" "" "6.500 ns" { adc_3:inst10|data_out[0] data_out1[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.500 ns" { adc_3:inst10|data_out[0] data_out1[0] } { 0.000ns 2.300ns } { 0.000ns 4.200ns } } }  } 0}  } { { "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" "" { Report "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc.quartus_db" { Floorplan "D:/altera/qdesigns50/zdx/ADC模块_r/adc/" "" "4.300 ns" { ad_sts adc_3:inst10|data_out[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "4.300 ns" { ad_sts ad_sts~out adc_3:inst10|data_out[0] } { 0.000ns 0.000ns 2.300ns } { 0.000ns 2.000ns 0.000ns } } } { "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" "" { Report "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc.quartus_db" { Floorplan "D:/altera/qdesigns50/zdx/ADC模块_r/adc/" "" "6.500 ns" { adc_3:inst10|data_out[0] data_out1[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.500 ns" { adc_3:inst10|data_out[0] data_out1[0] } { 0.000ns 2.300ns } { 0.000ns 4.200ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "adc_3:inst10\|data_out\[1\] data_in\[1\] ad_sts 1.100 ns register " "Info: th for register \"adc_3:inst10\|data_out\[1\]\" (data pin = \"data_in\[1\]\", clock pin = \"ad_sts\") is 1.100 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "ad_sts destination 4.300 ns + Longest register " "Info: + Longest clock path from clock \"ad_sts\" to destination register is 4.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns ad_sts 1 CLK PIN_103 13 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_103; Fanout = 13; CLK Node = 'ad_sts'" {  } { { "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" "" { Report "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc.quartus_db" { Floorplan "D:/altera/qdesigns50/zdx/ADC模块_r/adc/" "" "" { ad_sts } "NODE_NAME" } "" } } { "../adc_4/adc.bdf" "" { Schematic "D:/altera/qdesigns50/zdx/ADC模块_r/adc_4/adc.bdf" { { 32 -24 144 48 "ad_sts" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.300 ns) + CELL(0.000 ns) 4.300 ns adc_3:inst10\|data_out\[1\] 2 REG LC2_D12 1 " "Info: 2: + IC(2.300 ns) + CELL(0.000 ns) = 4.300 ns; Loc. = LC2_D12; Fanout = 1; REG Node = 'adc_3:inst10\|data_out\[1\]'" {  } { { "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" "" { Report "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc.quartus_db" { Floorplan "D:/altera/qdesigns50/zdx/ADC模块_r/adc/" "" "2.300 ns" { ad_sts adc_3:inst10|data_out[1] } "NODE_NAME" } "" } } { "../adc_3/adc_3.v" "" { Text "D:/altera/qdesigns50/zdx/ADC模块_r/adc_3/adc_3.v" 5 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns 46.51 % " "Info: Total cell delay = 2.000 ns ( 46.51 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.300 ns 53.49 % " "Info: Total interconnect delay = 2.300 ns ( 53.49 % )" {  } {  } 0}  } { { "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" "" { Report "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc.quartus_db" { Floorplan "D:/altera/qdesigns50/zdx/ADC模块_r/adc/" "" "4.300 ns" { ad_sts adc_3:inst10|data_out[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "4.300 ns" { ad_sts ad_sts~out adc_3:inst10|data_out[1] } { 0.000ns 0.000ns 2.300ns } { 0.000ns 2.000ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.500 ns + " "Info: + Micro hold delay of destination is 0.500 ns" {  } { { "../adc_3/adc_3.v" "" { Text "D:/altera/qdesigns50/zdx/ADC模块_r/adc_3/adc_3.v" 5 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.700 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns data_in\[1\] 1 PIN PIN_90 1 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_90; Fanout = 1; PIN Node = 'data_in\[1\]'" {  } { { "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" "" { Report "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc.quartus_db" { Floorplan "D:/altera/qdesigns50/zdx/ADC模块_r/adc/" "" "" { data_in[1] } "NODE_NAME" } "" } } { "../adc_4/adc.bdf" "" { Schematic "D:/altera/qdesigns50/zdx/ADC模块_r/adc_4/adc.bdf" { { 464 624 792 480 "data_in\[11..0\]" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(0.100 ns) 3.700 ns adc_3:inst10\|data_out\[1\] 2 REG LC2_D12 1 " "Info: 2: + IC(1.600 ns) + CELL(0.100 ns) = 3.700 ns; Loc. = LC2_D12; Fanout = 1; REG Node = 'adc_3:inst10\|data_out\[1\]'" {  } { { "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" "" { Report "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc.quartus_db" { Floorplan "D:/altera/qdesigns50/zdx/ADC模块_r/adc/" "" "1.700 ns" { data_in[1] adc_3:inst10|data_out[1] } "NODE_NAME" } "" } } { "../adc_3/adc_3.v" "" { Text "D:/altera/qdesigns50/zdx/ADC模块_r/adc_3/adc_3.v" 5 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.100 ns 56.76 % " "Info: Total cell delay = 2.100 ns ( 56.76 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.600 ns 43.24 % " "Info: Total interconnect delay = 1.600 ns ( 43.24 % )" {  } {  } 0}  } { { "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" "" { Report "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc.quartus_db" { Floorplan "D:/altera/qdesigns50/zdx/ADC模块_r/adc/" "" "3.700 ns" { data_in[1] adc_3:inst10|data_out[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.700 ns" { data_in[1] data_in[1]~out adc_3:inst10|data_out[1] } { 0.000ns 0.000ns 1.600ns } { 0.000ns 2.000ns 0.100ns } } }  } 0}  } { { "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" "" { Report "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc.quartus_db" { Floorplan "D:/altera/qdesigns50/zdx/ADC模块_r/adc/" "" "4.300 ns" { ad_sts adc_3:inst10|data_out[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "4.300 ns" { ad_sts ad_sts~out adc_3:inst10|data_out[1] } { 0.000ns 0.000ns 2.300ns } { 0.000ns 2.000ns 0.000ns } } } { "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" "" { Report "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc.quartus_db" { Floorplan "D:/altera/qdesigns50/zdx/ADC模块_r/adc/" "" "3.700 ns" { data_in[1] adc_3:inst10|data_out[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.700 ns" { data_in[1] data_in[1]~out adc_3:inst10|data_out[1] } { 0.000ns 0.000ns 1.600ns } { 0.000ns 2.000ns 0.100ns } } }  } 0}
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