adc.tan.qmsg

用verilog编程实现的基于FPGA的AD数据采集程序

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "../adc_4/adc.bdf" "" { Schematic "D:/altera/qdesigns50/zdx/ADC模块_r/adc_4/adc.bdf" { { -144 32 200 -128 "clk" "" } } } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "ad_sts " "Info: Assuming node \"ad_sts\" is an undefined clock" {  } { { "../adc_4/adc.bdf" "" { Schematic "D:/altera/qdesigns50/zdx/ADC模块_r/adc_4/adc.bdf" { { 32 -24 144 48 "ad_sts" "" } } } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "ad_sts" } } } }  } 0}  } {  } 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "did:inst3\|CLK_OUT " "Info: Detected ripple clock \"did:inst3\|CLK_OUT\" as buffer" {  } { { "../did.v" "" { Text "D:/altera/qdesigns50/zdx/ADC模块_r/did.v" 3 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "did:inst3\|CLK_OUT" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register adc_1:inst\|flag adc_1:inst\|flag 333.33 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 333.33 MHz between source register \"adc_1:inst\|flag\" and destination register \"adc_1:inst\|flag\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.5 ns 1.5 ns 3.0 ns " "Info: fmax restricted to Clock High delay (1.5 ns) plus Clock Low delay (1.5 ns) : restricted to 3.0 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.500 ns + Longest register register " "Info: + Longest register to register delay is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns adc_1:inst\|flag 1 REG LC4_H2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4_H2; Fanout = 2; REG Node = 'adc_1:inst\|flag'" {  } { { "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" "" { Report "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc.quartus_db" { Floorplan "D:/altera/qdesigns50/zdx/ADC模块_r/adc/" "" "" { adc_1:inst|flag } "NODE_NAME" } "" } } { "../adc_1/adc_1.v" "" { Text "D:/altera/qdesigns50/zdx/ADC模块_r/adc_1/adc_1.v" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.500 ns) 0.900 ns adc_1:inst\|always0~0 2 COMB LC6_H2 1 " "Info: 2: + IC(0.400 ns) + CELL(0.500 ns) = 0.900 ns; Loc. = LC6_H2; Fanout = 1; COMB Node = 'adc_1:inst\|always0~0'" {  } { { "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" "" { Report "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc.quartus_db" { Floorplan "D:/altera/qdesigns50/zdx/ADC模块_r/adc/" "" "0.900 ns" { adc_1:inst|flag adc_1:inst|always0~0 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.200 ns) 1.500 ns adc_1:inst\|flag 3 REG LC4_H2 2 " "Info: 3: + IC(0.400 ns) + CELL(0.200 ns) = 1.500 ns; Loc. = LC4_H2; Fanout = 2; REG Node = 'adc_1:inst\|flag'" {  } { { "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" "" { Report "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc.quartus_db" { Floorplan "D:/altera/qdesigns50/zdx/ADC模块_r/adc/" "" "0.600 ns" { adc_1:inst|always0~0 adc_1:inst|flag } "NODE_NAME" } "" } } { "../adc_1/adc_1.v" "" { Text "D:/altera/qdesigns50/zdx/ADC模块_r/adc_1/adc_1.v" 7 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.700 ns 46.67 % " "Info: Total cell delay = 0.700 ns ( 46.67 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.800 ns 53.33 % " "Info: Total interconnect delay = 0.800 ns ( 53.33 % )" {  } {  } 0}  } { { "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" "" { Report "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc.quartus_db" { Floorplan "D:/altera/qdesigns50/zdx/ADC模块_r/adc/" "" "1.500 ns" { adc_1:inst|flag adc_1:inst|always0~0 adc_1:inst|flag } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "1.500 ns" { adc_1:inst|flag adc_1:inst|always0~0 adc_1:inst|flag } { 0.000ns 0.400ns 0.400ns } { 0.000ns 0.500ns 0.200ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.700 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 0.300 ns clk 1 CLK PIN_79 4 " "Info: 1: + IC(0.000 ns) + CELL(0.300 ns) = 0.300 ns; Loc. = PIN_79; Fanout = 4; CLK Node = 'clk'" {  } { { "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" "" { Report "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc.quartus_db" { Floorplan "D:/altera/qdesigns50/zdx/ADC模块_r/adc/" "" "" { clk } "NODE_NAME" } "" } } { "../adc_4/adc.bdf" "" { Schematic "D:/altera/qdesigns50/zdx/ADC模块_r/adc_4/adc.bdf" { { -144 32 200 -128 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.800 ns) + CELL(0.600 ns) 1.700 ns did:inst3\|CLK_OUT 2 REG LC1_F26 2 " "Info: 2: + IC(0.800 ns) + CELL(0.600 ns) = 1.700 ns; Loc. = LC1_F26; Fanout = 2; REG Node = 'did:inst3\|CLK_OUT'" {  } { { "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" "" { Report "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc.quartus_db" { Floorplan "D:/altera/qdesigns50/zdx/ADC模块_r/adc/" "" "1.400 ns" { clk did:inst3|CLK_OUT } "NODE_NAME" } "" } } { "../did.v" "" { Text "D:/altera/qdesigns50/zdx/ADC模块_r/did.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.000 ns) 3.700 ns adc_1:inst\|flag 3 REG LC4_H2 2 " "Info: 3: + IC(2.000 ns) + CELL(0.000 ns) = 3.700 ns; Loc. = LC4_H2; Fanout = 2; REG Node = 'adc_1:inst\|flag'" {  } { { "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" "" { Report "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc.quartus_db" { Floorplan "D:/altera/qdesigns50/zdx/ADC模块_r/adc/" "" "2.000 ns" { did:inst3|CLK_OUT adc_1:inst|flag } "NODE_NAME" } "" } } { "../adc_1/adc_1.v" "" { Text "D:/altera/qdesigns50/zdx/ADC模块_r/adc_1/adc_1.v" 7 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.900 ns 24.32 % " "Info: Total cell delay = 0.900 ns ( 24.32 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.800 ns 75.68 % " "Info: Total interconnect delay = 2.800 ns ( 75.68 % )" {  } {  } 0}  } { { "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" "" { Report "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc.quartus_db" { Floorplan "D:/altera/qdesigns50/zdx/ADC模块_r/adc/" "" "3.700 ns" { clk did:inst3|CLK_OUT adc_1:inst|flag } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.700 ns" { clk clk~out did:inst3|CLK_OUT adc_1:inst|flag } { 0.000ns 0.000ns 0.800ns 2.000ns } { 0.000ns 0.300ns 0.600ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.700 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 0.300 ns clk 1 CLK PIN_79 4 " "Info: 1: + IC(0.000 ns) + CELL(0.300 ns) = 0.300 ns; Loc. = PIN_79; Fanout = 4; CLK Node = 'clk'" {  } { { "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" "" { Report "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc.quartus_db" { Floorplan "D:/altera/qdesigns50/zdx/ADC模块_r/adc/" "" "" { clk } "NODE_NAME" } "" } } { "../adc_4/adc.bdf" "" { Schematic "D:/altera/qdesigns50/zdx/ADC模块_r/adc_4/adc.bdf" { { -144 32 200 -128 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.800 ns) + CELL(0.600 ns) 1.700 ns did:inst3\|CLK_OUT 2 REG LC1_F26 2 " "Info: 2: + IC(0.800 ns) + CELL(0.600 ns) = 1.700 ns; Loc. = LC1_F26; Fanout = 2; REG Node = 'did:inst3\|CLK_OUT'" {  } { { "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" "" { Report "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc.quartus_db" { Floorplan "D:/altera/qdesigns50/zdx/ADC模块_r/adc/" "" "1.400 ns" { clk did:inst3|CLK_OUT } "NODE_NAME" } "" } } { "../did.v" "" { Text "D:/altera/qdesigns50/zdx/ADC模块_r/did.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.000 ns) 3.700 ns adc_1:inst\|flag 3 REG LC4_H2 2 " "Info: 3: + IC(2.000 ns) + CELL(0.000 ns) = 3.700 ns; Loc. = LC4_H2; Fanout = 2; REG Node = 'adc_1:inst\|flag'" {  } { { "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" "" { Report "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc.quartus_db" { Floorplan "D:/altera/qdesigns50/zdx/ADC模块_r/adc/" "" "2.000 ns" { did:inst3|CLK_OUT adc_1:inst|flag } "NODE_NAME" } "" } } { "../adc_1/adc_1.v" "" { Text "D:/altera/qdesigns50/zdx/ADC模块_r/adc_1/adc_1.v" 7 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.900 ns 24.32 % " "Info: Total cell delay = 0.900 ns ( 24.32 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.800 ns 75.68 % " "Info: Total interconnect delay = 2.800 ns ( 75.68 % )" {  } {  } 0}  } { { "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" "" { Report "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc.quartus_db" { Floorplan "D:/altera/qdesigns50/zdx/ADC模块_r/adc/" "" "3.700 ns" { clk did:inst3|CLK_OUT adc_1:inst|flag } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.700 ns" { clk clk~out did:inst3|CLK_OUT adc_1:inst|flag } { 0.000ns 0.000ns 0.800ns 2.000ns } { 0.000ns 0.300ns 0.600ns 0.000ns } } }  } 0}  } { { "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" "" { Report "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc.quartus_db" { Floorplan "D:/altera/qdesigns50/zdx/ADC模块_r/adc/" "" "3.700 ns" { clk did:inst3|CLK_OUT adc_1:inst|flag } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.700 ns" { clk clk~out did:inst3|CLK_OUT adc_1:inst|flag } { 0.000ns 0.000ns 0.800ns 2.000ns } { 0.000ns 0.300ns 0.600ns 0.000ns } } } { "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" "" { Report "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc.quartus_db" { Floorplan "D:/altera/qdesigns50/zdx/ADC模块_r/adc/" "" "3.700 ns" { clk did:inst3|CLK_OUT adc_1:inst|flag } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.700 ns" { clk clk~out did:inst3|CLK_OUT adc_1:inst|flag } { 0.000ns 0.000ns 0.800ns 2.000ns } { 0.000ns 0.300ns 0.600ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.600 ns + " "Info: + Micro clock to output delay of source is 0.600 ns" {  } { { "../adc_1/adc_1.v" "" { Text "D:/altera/qdesigns50/zdx/ADC模块_r/adc_1/adc_1.v" 7 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.400 ns + " "Info: + Micro setup delay of destination is 0.400 ns" {  } { { "../adc_1/adc_1.v" "" { Text "D:/altera/qdesigns50/zdx/ADC模块_r/adc_1/adc_1.v" 7 -1 0 } }  } 0}  } { { "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" "" { Report "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc.quartus_db" { Floorplan "D:/altera/qdesigns50/zdx/ADC模块_r/adc/" "" "1.500 ns" { adc_1:inst|flag adc_1:inst|always0~0 adc_1:inst|flag } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "1.500 ns" { adc_1:inst|flag adc_1:inst|always0~0 adc_1:inst|flag } { 0.000ns 0.400ns 0.400ns } { 0.000ns 0.500ns 0.200ns } } } { "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" "" { Report "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc.quartus_db" { Floorplan "D:/altera/qdesigns50/zdx/ADC模块_r/adc/" "" "3.700 ns" { clk did:inst3|CLK_OUT adc_1:inst|flag } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.700 ns" { clk clk~out did:inst3|CLK_OUT adc_1:inst|flag } { 0.000ns 0.000ns 0.800ns 2.000ns } { 0.000ns 0.300ns 0.600ns 0.000ns } } } { "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" "" { Report "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc.quartus_db" { Floorplan "D:/altera/qdesigns50/zdx/ADC模块_r/adc/" "" "3.700 ns" { clk did:inst3|CLK_OUT adc_1:inst|flag } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.700 ns" { clk clk~out did:inst3|CLK_OUT adc_1:inst|flag } { 0.000ns 0.000ns 0.800ns 2.000ns } { 0.000ns 0.300ns 0.600ns 0.000ns } } }  } 0}  } { { "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" "" { Report "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "D:/altera/qdesigns50/zdx/ADC模块_r/adc/db/adc.quartus_db" { Floorplan "D:/altera/qdesigns50/zdx/ADC模块_r/adc/" "" "" { adc_1:inst|flag } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { adc_1:inst|flag } {  } {  } } } { "../adc_1/adc_1.v" "" { Text "D:/altera/qdesigns50/zdx/ADC模块_r/adc_1/adc_1.v" 7 -1 0 } }  } 0}