adc.hif

用verilog编程实现的基于FPGA的AD数据采集程序

Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version
2
45
OFF
OFF
OFF
OFF
OFF
FV_OFF
VRSM_ON
VHSM_ON
0
# entity
adc
# case_insensitive
# source_file
..|adc_4|adc.bdf
1198248044
23
# storage
db|adc.(0).cnf
db|adc.(0).cnf
# hierarchies {
|
}
# end
# entity
did
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
..|did.v
1198247970
7
# storage
db|adc.(2).cnf
db|adc.(2).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
did:inst3
}
# end
# entity
adc_4
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
..|adc_4|adc_4.v
1198245742
7
# storage
db|adc.(3).cnf
db|adc.(3).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
adc_4:inst11
}
# end
# entity
adc_3
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
..|adc_3|adc_3.v
1196944658
7
# storage
db|adc.(4).cnf
db|adc.(4).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
adc_3:inst10
adc_3:inst9
adc_3:inst8
adc_3:inst2
adc_3:inst4
adc_3:inst5
adc_3:inst6
adc_3:inst14
}
# end
# entity
adc_2
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
..|adc_2|adc_2.v
1196934252
7
# storage
db|adc.(5).cnf
db|adc.(5).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
adc_2:inst1
}
# end
# entity
lpm_add_sub
# case_insensitive
# source_file
..|..|..|..|quartus50|libraries|megafunctions|lpm_add_sub.tdf
1114012446
6
# storage
db|adc.(6).cnf
db|adc.(6).cnf
# user_parameter {
LPM_WIDTH
5
PARAMETER_UNKNOWN
USR
LPM_REPRESENTATION
UNSIGNED
PARAMETER_UNKNOWN
USR
LPM_DIRECTION
ADD
PARAMETER_UNKNOWN
USR
ONE_INPUT_IS_CONSTANT
YES
PARAMETER_UNKNOWN
USR
LPM_PIPELINE
0
PARAMETER_UNKNOWN
DEF
MAXIMIZE_SPEED
5
PARAMETER_UNKNOWN
DEF
REGISTERED_AT_END
0
PARAMETER_UNKNOWN
DEF
OPTIMIZE_FOR_SPEED
1
PARAMETER_UNKNOWN
USR
USE_CS_BUFFERS
1
PARAMETER_UNKNOWN
DEF
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
CARRY_CHAIN_LENGTH
48
CARRY_CHAIN_LENGTH
USR
DEVICE_FAMILY
ACEX1K
PARAMETER_UNKNOWN
USR
USE_WYS
OFF
PARAMETER_UNKNOWN
DEF
STYLE
FAST
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
add_sub_llh
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
cin
dataa0
dataa1
dataa2
dataa3
dataa4
datab0
datab1
datab2
datab3
datab4
result0
result1
result2
result3
result4
}
# include_file {
..|..|..|..|quartus50|libraries|megafunctions|addcore.inc
1107572218
..|..|..|..|quartus50|libraries|megafunctions|look_add.inc
1107574364
..|..|..|..|quartus50|libraries|megafunctions|bypassff.inc
1107573920
..|..|..|..|quartus50|libraries|megafunctions|altshift.inc
1107573438
..|..|..|..|quartus50|libraries|megafunctions|aglobal50.inc
1131033050
..|..|..|..|quartus50|libraries|megafunctions|alt_stratix_add_sub.inc
1107572606
..|..|..|..|quartus50|libraries|megafunctions|alt_mercury_add_sub.inc
1107572592
}
# end
# entity
addcore
# case_insensitive
# source_file
..|..|..|..|quartus50|libraries|megafunctions|addcore.tdf
1114012446
6
# storage
db|adc.(7).cnf
db|adc.(7).cnf
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
width
5
PARAMETER_UNKNOWN
USR
REPRESENTATION
UNSIGNED
PARAMETER_UNKNOWN
USR
DIRECTION
ADD
PARAMETER_UNKNOWN
USR
USE_CS_BUFFERS
1
PARAMETER_UNKNOWN
USR
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
CARRY_CHAIN_LENGTH
48
CARRY_CHAIN_LENGTH
USR
DEVICE_FAMILY
ACEX1K
PARAMETER_UNKNOWN
USR
}
# used_port {
dataa0
dataa1
dataa2
dataa3
dataa4
datab0
datab1
datab2
datab3
datab4
cin
result0
result1
result2
result3
result4
}
# include_file {
..|..|..|..|quartus50|libraries|megafunctions|addcore.inc
1107572218
..|..|..|..|quartus50|libraries|megafunctions|aglobal50.inc
1131033050
..|..|..|..|quartus50|libraries|megafunctions|a_csnbuffer.inc
1107571892
}
# end
# entity
a_csnbuffer
# case_insensitive
# source_file
..|..|..|..|quartus50|libraries|megafunctions|a_csnbuffer.tdf
1114012448
6
# storage
db|adc.(8).cnf
db|adc.(8).cnf
# user_parameter {
WIDTH
5
PARAMETER_UNKNOWN
USR
NEED_CARRY
0
PARAMETER_UNKNOWN
DEF
USE_CS_BUFFERS
1
PARAMETER_UNKNOWN
USR
}
# used_port {
sin0
sout0
}
# end
# entity
a_csnbuffer
# case_insensitive
# source_file
..|..|..|..|quartus50|libraries|megafunctions|a_csnbuffer.tdf
1114012448
6
# storage
db|adc.(9).cnf
db|adc.(9).cnf
# user_parameter {
WIDTH
5
PARAMETER_UNKNOWN
USR
NEED_CARRY
1
PARAMETER_UNKNOWN
USR
USE_CS_BUFFERS
1
PARAMETER_UNKNOWN
USR
}
# used_port {
sin0
sin1
sin2
sin3
sin4
cin0
cin1
cin2
cin3
cin4
sout0
sout1
sout2
sout3
sout4
cout0
cout1
cout2
cout3
cout4
}
# end
# entity
altshift
# case_insensitive
# source_file
..|..|..|..|quartus50|libraries|megafunctions|altshift.tdf
1114012454
6
# storage
db|adc.(10).cnf
db|adc.(10).cnf
# user_parameter {
WIDTH
5
PARAMETER_UNKNOWN
USR
DEPTH
0
PARAMETER_UNKNOWN
USR
}
# used_port {
data0
data1
data2
data3
data4
result0
result1
result2
result3
result4
}
# end
# entity
altshift
# case_insensitive
# source_file
..|..|..|..|quartus50|libraries|megafunctions|altshift.tdf
1114012454
6
# storage
db|adc.(11).cnf
db|adc.(11).cnf
# user_parameter {
WIDTH
1
PARAMETER_UNKNOWN
USR
DEPTH
0
PARAMETER_UNKNOWN
USR
}
# used_port {
data0
result0
}
# end
# entity
adc_1
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
..|adc_1|adc_1.v
1198898466
7
# storage
db|adc.(1).cnf
db|adc.(1).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
adc_1:inst
}
# end
# complete