adc.hier_info

用verilog编程实现的基于FPGA的AD数据采集程序

|adc
control <= adc_1:inst.control
clk => did:inst3.CLK
ad_sts => adc_4:inst11.ad_sts
ad_sts => adc_3:inst10.ad_sts
ad_sts => adc_3:inst9.ad_sts
ad_sts => adc_3:inst8.ad_sts
ad_sts => adc_3:inst2.ad_sts
ad_sts => adc_3:inst4.ad_sts
ad_sts => adc_3:inst5.ad_sts
ad_sts => adc_3:inst6.ad_sts
ad_sts => adc_3:inst14.ad_sts
add_out1[0] <= adc_1:inst.add_out[0]
add_out1[1] <= adc_1:inst.add_out[1]
add_out1[2] <= adc_1:inst.add_out[2]
data_out1[0] <= adc_3:inst10.data_out[0]
data_out1[1] <= adc_3:inst10.data_out[1]
data_out1[2] <= adc_3:inst10.data_out[2]
data_out1[3] <= adc_3:inst10.data_out[3]
data_out1[4] <= adc_3:inst10.data_out[4]
data_out1[5] <= adc_3:inst10.data_out[5]
data_out1[6] <= adc_3:inst10.data_out[6]
data_out1[7] <= adc_3:inst10.data_out[7]
data_out1[8] <= adc_3:inst10.data_out[8]
data_out1[9] <= adc_3:inst10.data_out[9]
data_out1[10] <= adc_3:inst10.data_out[10]
data_out1[11] <= adc_3:inst10.data_out[11]
data_in[0] => adc_3:inst10.data_in[0]
data_in[0] => adc_3:inst9.data_in[0]
data_in[0] => adc_3:inst8.data_in[0]
data_in[0] => adc_3:inst2.data_in[0]
data_in[0] => adc_3:inst4.data_in[0]
data_in[0] => adc_3:inst5.data_in[0]
data_in[0] => adc_3:inst6.data_in[0]
data_in[0] => adc_3:inst14.data_in[0]
data_in[1] => adc_3:inst10.data_in[1]
data_in[1] => adc_3:inst9.data_in[1]
data_in[1] => adc_3:inst8.data_in[1]
data_in[1] => adc_3:inst2.data_in[1]
data_in[1] => adc_3:inst4.data_in[1]
data_in[1] => adc_3:inst5.data_in[1]
data_in[1] => adc_3:inst6.data_in[1]
data_in[1] => adc_3:inst14.data_in[1]
data_in[2] => adc_3:inst10.data_in[2]
data_in[2] => adc_3:inst9.data_in[2]
data_in[2] => adc_3:inst8.data_in[2]
data_in[2] => adc_3:inst2.data_in[2]
data_in[2] => adc_3:inst4.data_in[2]
data_in[2] => adc_3:inst5.data_in[2]
data_in[2] => adc_3:inst6.data_in[2]
data_in[2] => adc_3:inst14.data_in[2]
data_in[3] => adc_3:inst10.data_in[3]
data_in[3] => adc_3:inst9.data_in[3]
data_in[3] => adc_3:inst8.data_in[3]
data_in[3] => adc_3:inst2.data_in[3]
data_in[3] => adc_3:inst4.data_in[3]
data_in[3] => adc_3:inst5.data_in[3]
data_in[3] => adc_3:inst6.data_in[3]
data_in[3] => adc_3:inst14.data_in[3]
data_in[4] => adc_3:inst10.data_in[4]
data_in[4] => adc_3:inst9.data_in[4]
data_in[4] => adc_3:inst8.data_in[4]
data_in[4] => adc_3:inst2.data_in[4]
data_in[4] => adc_3:inst4.data_in[4]
data_in[4] => adc_3:inst5.data_in[4]
data_in[4] => adc_3:inst6.data_in[4]
data_in[4] => adc_3:inst14.data_in[4]
data_in[5] => adc_3:inst10.data_in[5]
data_in[5] => adc_3:inst9.data_in[5]
data_in[5] => adc_3:inst8.data_in[5]
data_in[5] => adc_3:inst2.data_in[5]
data_in[5] => adc_3:inst4.data_in[5]
data_in[5] => adc_3:inst5.data_in[5]
data_in[5] => adc_3:inst6.data_in[5]
data_in[5] => adc_3:inst14.data_in[5]
data_in[6] => adc_3:inst10.data_in[6]
data_in[6] => adc_3:inst9.data_in[6]
data_in[6] => adc_3:inst8.data_in[6]
data_in[6] => adc_3:inst2.data_in[6]
data_in[6] => adc_3:inst4.data_in[6]
data_in[6] => adc_3:inst5.data_in[6]
data_in[6] => adc_3:inst6.data_in[6]
data_in[6] => adc_3:inst14.data_in[6]
data_in[7] => adc_3:inst10.data_in[7]
data_in[7] => adc_3:inst9.data_in[7]
data_in[7] => adc_3:inst8.data_in[7]
data_in[7] => adc_3:inst2.data_in[7]
data_in[7] => adc_3:inst4.data_in[7]
data_in[7] => adc_3:inst5.data_in[7]
data_in[7] => adc_3:inst6.data_in[7]
data_in[7] => adc_3:inst14.data_in[7]
data_in[8] => adc_3:inst10.data_in[8]
data_in[8] => adc_3:inst9.data_in[8]
data_in[8] => adc_3:inst8.data_in[8]
data_in[8] => adc_3:inst2.data_in[8]
data_in[8] => adc_3:inst4.data_in[8]
data_in[8] => adc_3:inst5.data_in[8]
data_in[8] => adc_3:inst6.data_in[8]
data_in[8] => adc_3:inst14.data_in[8]
data_in[9] => adc_3:inst10.data_in[9]
data_in[9] => adc_3:inst9.data_in[9]
data_in[9] => adc_3:inst8.data_in[9]
data_in[9] => adc_3:inst2.data_in[9]
data_in[9] => adc_3:inst4.data_in[9]
data_in[9] => adc_3:inst5.data_in[9]
data_in[9] => adc_3:inst6.data_in[9]
data_in[9] => adc_3:inst14.data_in[9]
data_in[10] => adc_3:inst10.data_in[10]
data_in[10] => adc_3:inst9.data_in[10]
data_in[10] => adc_3:inst8.data_in[10]
data_in[10] => adc_3:inst2.data_in[10]
data_in[10] => adc_3:inst4.data_in[10]
data_in[10] => adc_3:inst5.data_in[10]
data_in[10] => adc_3:inst6.data_in[10]
data_in[10] => adc_3:inst14.data_in[10]
data_in[11] => adc_3:inst10.data_in[11]
data_in[11] => adc_3:inst9.data_in[11]
data_in[11] => adc_3:inst8.data_in[11]
data_in[11] => adc_3:inst2.data_in[11]
data_in[11] => adc_3:inst4.data_in[11]
data_in[11] => adc_3:inst5.data_in[11]
data_in[11] => adc_3:inst6.data_in[11]
data_in[11] => adc_3:inst14.data_in[11]
data_out2[0] <= adc_3:inst9.data_out[0]
data_out2[1] <= adc_3:inst9.data_out[1]
data_out2[2] <= adc_3:inst9.data_out[2]
data_out2[3] <= adc_3:inst9.data_out[3]
data_out2[4] <= adc_3:inst9.data_out[4]
data_out2[5] <= adc_3:inst9.data_out[5]
data_out2[6] <= adc_3:inst9.data_out[6]
data_out2[7] <= adc_3:inst9.data_out[7]
data_out2[8] <= adc_3:inst9.data_out[8]
data_out2[9] <= adc_3:inst9.data_out[9]
data_out2[10] <= adc_3:inst9.data_out[10]
data_out2[11] <= adc_3:inst9.data_out[11]
data_out3[0] <= adc_3:inst8.data_out[0]
data_out3[1] <= adc_3:inst8.data_out[1]
data_out3[2] <= adc_3:inst8.data_out[2]
data_out3[3] <= adc_3:inst8.data_out[3]
data_out3[4] <= adc_3:inst8.data_out[4]
data_out3[5] <= adc_3:inst8.data_out[5]
data_out3[6] <= adc_3:inst8.data_out[6]
data_out3[7] <= adc_3:inst8.data_out[7]
data_out3[8] <= adc_3:inst8.data_out[8]
data_out3[9] <= adc_3:inst8.data_out[9]
data_out3[10] <= adc_3:inst8.data_out[10]
data_out3[11] <= adc_3:inst8.data_out[11]
data_out4[0] <= adc_3:inst2.data_out[0]
data_out4[1] <= adc_3:inst2.data_out[1]
data_out4[2] <= adc_3:inst2.data_out[2]
data_out4[3] <= adc_3:inst2.data_out[3]
data_out4[4] <= adc_3:inst2.data_out[4]
data_out4[5] <= adc_3:inst2.data_out[5]
data_out4[6] <= adc_3:inst2.data_out[6]
data_out4[7] <= adc_3:inst2.data_out[7]
data_out4[8] <= adc_3:inst2.data_out[8]
data_out4[9] <= adc_3:inst2.data_out[9]
data_out4[10] <= adc_3:inst2.data_out[10]
data_out4[11] <= adc_3:inst2.data_out[11]
data_out5[0] <= adc_3:inst4.data_out[0]
data_out5[1] <= adc_3:inst4.data_out[1]
data_out5[2] <= adc_3:inst4.data_out[2]
data_out5[3] <= adc_3:inst4.data_out[3]
data_out5[4] <= adc_3:inst4.data_out[4]
data_out5[5] <= adc_3:inst4.data_out[5]
data_out5[6] <= adc_3:inst4.data_out[6]
data_out5[7] <= adc_3:inst4.data_out[7]
data_out5[8] <= adc_3:inst4.data_out[8]
data_out5[9] <= adc_3:inst4.data_out[9]
data_out5[10] <= adc_3:inst4.data_out[10]
data_out5[11] <= adc_3:inst4.data_out[11]
data_out6[0] <= adc_3:inst5.data_out[0]
data_out6[1] <= adc_3:inst5.data_out[1]
data_out6[2] <= adc_3:inst5.data_out[2]
data_out6[3] <= adc_3:inst5.data_out[3]
data_out6[4] <= adc_3:inst5.data_out[4]
data_out6[5] <= adc_3:inst5.data_out[5]
data_out6[6] <= adc_3:inst5.data_out[6]
data_out6[7] <= adc_3:inst5.data_out[7]
data_out6[8] <= adc_3:inst5.data_out[8]
data_out6[9] <= adc_3:inst5.data_out[9]
data_out6[10] <= adc_3:inst5.data_out[10]
data_out6[11] <= adc_3:inst5.data_out[11]
data_out7[0] <= adc_3:inst6.data_out[0]
data_out7[1] <= adc_3:inst6.data_out[1]
data_out7[2] <= adc_3:inst6.data_out[2]
data_out7[3] <= adc_3:inst6.data_out[3]
data_out7[4] <= adc_3:inst6.data_out[4]
data_out7[5] <= adc_3:inst6.data_out[5]
data_out7[6] <= adc_3:inst6.data_out[6]
data_out7[7] <= adc_3:inst6.data_out[7]
data_out7[8] <= adc_3:inst6.data_out[8]
data_out7[9] <= adc_3:inst6.data_out[9]
data_out7[10] <= adc_3:inst6.data_out[10]
data_out7[11] <= adc_3:inst6.data_out[11]
data_out8[0] <= adc_3:inst14.data_out[0]
data_out8[1] <= adc_3:inst14.data_out[1]
data_out8[2] <= adc_3:inst14.data_out[2]
data_out8[3] <= adc_3:inst14.data_out[3]
data_out8[4] <= adc_3:inst14.data_out[4]
data_out8[5] <= adc_3:inst14.data_out[5]
data_out8[6] <= adc_3:inst14.data_out[6]
data_out8[7] <= adc_3:inst14.data_out[7]
data_out8[8] <= adc_3:inst14.data_out[8]
data_out8[9] <= adc_3:inst14.data_out[9]
data_out8[10] <= adc_3:inst14.data_out[10]
data_out8[11] <= adc_3:inst14.data_out[11]


|adc|adc_1:inst
clk => beg.CLK
clk => flag.CLK
clk => control~reg0.CLK
f_r => always0~0.IN1
f_r => flag~0.DATAA
add[0] <= <VCC>
add[1] <= <VCC>
add[2] <= <VCC>
add_out[0] <= <GND>
add_out[1] <= <GND>
add_out[2] <= <GND>
control <= control~reg0.DB_MAX_OUTPUT_PORT_TYPE


|adc|did:inst3
CLK => num[1].CLK
CLK => num[0].CLK
CLK => CLK_OUT~reg0.CLK
CLK => num[2].CLK
CLK_OUT <= CLK_OUT~reg0.DB_MAX_OUTPUT_PORT_TYPE


|adc|adc_4:inst11
ad_sts => f_r~reg0.CLK
f_r <= f_r~reg0.DB_MAX_OUTPUT_PORT_TYPE


|adc|adc_3:inst10
sel => data_out[11]~reg0.ENA
sel => data_out[10]~reg0.ENA
sel => data_out[9]~reg0.ENA
sel => data_out[8]~reg0.ENA
sel => data_out[7]~reg0.ENA
sel => data_out[6]~reg0.ENA
sel => data_out[5]~reg0.ENA
sel => data_out[4]~reg0.ENA
sel => data_out[3]~reg0.ENA
sel => data_out[2]~reg0.ENA
sel => data_out[1]~reg0.ENA
sel => data_out[0]~reg0.ENA
ad_sts => data_out[11]~reg0.CLK
ad_sts => data_out[10]~reg0.CLK
ad_sts => data_out[9]~reg0.CLK
ad_sts => data_out[8]~reg0.CLK
ad_sts => data_out[7]~reg0.CLK
ad_sts => data_out[6]~reg0.CLK
ad_sts => data_out[5]~reg0.CLK
ad_sts => data_out[4]~reg0.CLK
ad_sts => data_out[3]~reg0.CLK
ad_sts => data_out[2]~reg0.CLK
ad_sts => data_out[1]~reg0.CLK
ad_sts => data_out[0]~reg0.CLK
data_in[0] => data_out[0]~reg0.DATAIN
data_in[1] => data_out[1]~reg0.DATAIN
data_in[2] => data_out[2]~reg0.DATAIN
data_in[3] => data_out[3]~reg0.DATAIN
data_in[4] => data_out[4]~reg0.DATAIN
data_in[5] => data_out[5]~reg0.DATAIN
data_in[6] => data_out[6]~reg0.DATAIN
data_in[7] => data_out[7]~reg0.DATAIN
data_in[8] => data_out[8]~reg0.DATAIN
data_in[9] => data_out[9]~reg0.DATAIN
data_in[10] => data_out[10]~reg0.DATAIN
data_in[11] => data_out[11]~reg0.DATAIN
data_out[0] <= data_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[1] <= data_out[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[2] <= data_out[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[3] <= data_out[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[4] <= data_out[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[5] <= data_out[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[6] <= data_out[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[7] <= data_out[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[8] <= data_out[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[9] <= data_out[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[10] <= data_out[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[11] <= data_out[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|adc|adc_2:inst1
add[0] => Decoder~0.IN2
add[1] => Decoder~0.IN1
add[2] => Decoder~0.IN0
sel1 <= Decoder~0.DB_MAX_OUTPUT_PORT_TYPE
sel2 <= Decoder~0.DB_MAX_OUTPUT_PORT_TYPE
sel3 <= Decoder~0.DB_MAX_OUTPUT_PORT_TYPE
sel4 <= Decoder~0.DB_MAX_OUTPUT_PORT_TYPE
sel5 <= Decoder~0.DB_MAX_OUTPUT_PORT_TYPE
sel6 <= Decoder~0.DB_MAX_OUTPUT_PORT_TYPE
sel7 <= Decoder~0.DB_MAX_OUTPUT_PORT_TYPE
sel8 <= Decoder~0.DB_MAX_OUTPUT_PORT_TYPE


|adc|adc_3:inst9
sel => data_out[11]~reg0.ENA
sel => data_out[10]~reg0.ENA
sel => data_out[9]~reg0.ENA
sel => data_out[8]~reg0.ENA
sel => data_out[7]~reg0.ENA
sel => data_out[6]~reg0.ENA
sel => data_out[5]~reg0.ENA
sel => data_out[4]~reg0.ENA
sel => data_out[3]~reg0.ENA
sel => data_out[2]~reg0.ENA
sel => data_out[1]~reg0.ENA
sel => data_out[0]~reg0.ENA
ad_sts => data_out[11]~reg0.CLK
ad_sts => data_out[10]~reg0.CLK
ad_sts => data_out[9]~reg0.CLK
ad_sts => data_out[8]~reg0.CLK
ad_sts => data_out[7]~reg0.CLK
ad_sts => data_out[6]~reg0.CLK
ad_sts => data_out[5]~reg0.CLK
ad_sts => data_out[4]~reg0.CLK
ad_sts => data_out[3]~reg0.CLK
ad_sts => data_out[2]~reg0.CLK
ad_sts => data_out[1]~reg0.CLK
ad_sts => data_out[0]~reg0.CLK
data_in[0] => data_out[0]~reg0.DATAIN
data_in[1] => data_out[1]~reg0.DATAIN
data_in[2] => data_out[2]~reg0.DATAIN