adc.tan.rpt

用verilog编程实现的基于FPGA的AD数据采集程序

+-------+--------------+------------+---------------------------+---------------+------------+
; Slack ; Required tco ; Actual tco ; From                      ; To            ; From Clock ;
+-------+--------------+------------+---------------------------+---------------+------------+
; N/A   ; None         ; 11.400 ns  ; adc_3:inst10|data_out[0]  ; data_out1[0]  ; ad_sts     ;
; N/A   ; None         ; 11.400 ns  ; adc_3:inst10|data_out[1]  ; data_out1[1]  ; ad_sts     ;
; N/A   ; None         ; 10.300 ns  ; adc_3:inst10|data_out[7]  ; data_out1[7]  ; ad_sts     ;
; N/A   ; None         ; 10.300 ns  ; adc_3:inst10|data_out[10] ; data_out1[10] ; ad_sts     ;
; N/A   ; None         ; 10.300 ns  ; adc_3:inst10|data_out[11] ; data_out1[11] ; ad_sts     ;
; N/A   ; None         ; 10.200 ns  ; adc_3:inst10|data_out[4]  ; data_out1[4]  ; ad_sts     ;
; N/A   ; None         ; 9.800 ns   ; adc_3:inst10|data_out[3]  ; data_out1[3]  ; ad_sts     ;
; N/A   ; None         ; 9.800 ns   ; adc_3:inst10|data_out[6]  ; data_out1[6]  ; ad_sts     ;
; N/A   ; None         ; 9.800 ns   ; adc_3:inst10|data_out[8]  ; data_out1[8]  ; ad_sts     ;
; N/A   ; None         ; 9.300 ns   ; adc_3:inst10|data_out[9]  ; data_out1[9]  ; ad_sts     ;
; N/A   ; None         ; 9.200 ns   ; adc_1:inst|control        ; control       ; clk        ;
; N/A   ; None         ; 8.800 ns   ; adc_3:inst10|data_out[2]  ; data_out1[2]  ; ad_sts     ;
; N/A   ; None         ; 8.800 ns   ; adc_3:inst10|data_out[5]  ; data_out1[5]  ; ad_sts     ;
+-------+--------------+------------+---------------------------+---------------+------------+


+----------------------------------------------------------------------------------------------+
; th                                                                                           ;
+---------------+-------------+-----------+-------------+---------------------------+----------+
; Minimum Slack ; Required th ; Actual th ; From        ; To                        ; To Clock ;
+---------------+-------------+-----------+-------------+---------------------------+----------+
; N/A           ; None        ; 1.100 ns  ; data_in[1]  ; adc_3:inst10|data_out[1]  ; ad_sts   ;
; N/A           ; None        ; 0.400 ns  ; data_in[0]  ; adc_3:inst10|data_out[0]  ; ad_sts   ;
; N/A           ; None        ; 0.400 ns  ; data_in[4]  ; adc_3:inst10|data_out[4]  ; ad_sts   ;
; N/A           ; None        ; 0.400 ns  ; data_in[6]  ; adc_3:inst10|data_out[6]  ; ad_sts   ;
; N/A           ; None        ; 0.400 ns  ; data_in[7]  ; adc_3:inst10|data_out[7]  ; ad_sts   ;
; N/A           ; None        ; 0.300 ns  ; data_in[9]  ; adc_3:inst10|data_out[9]  ; ad_sts   ;
; N/A           ; None        ; 0.300 ns  ; data_in[10] ; adc_3:inst10|data_out[10] ; ad_sts   ;
; N/A           ; None        ; 0.200 ns  ; data_in[11] ; adc_3:inst10|data_out[11] ; ad_sts   ;
; N/A           ; None        ; 0.100 ns  ; data_in[5]  ; adc_3:inst10|data_out[5]  ; ad_sts   ;
; N/A           ; None        ; 0.100 ns  ; data_in[8]  ; adc_3:inst10|data_out[8]  ; ad_sts   ;
; N/A           ; None        ; 0.000 ns  ; data_in[2]  ; adc_3:inst10|data_out[2]  ; ad_sts   ;
; N/A           ; None        ; 0.000 ns  ; data_in[3]  ; adc_3:inst10|data_out[3]  ; ad_sts   ;
+---------------+-------------+-----------+-------------+---------------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version
    Info: Processing started: Sat Dec 29 11:21:28 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off adc -c adc
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
    Info: Assuming node "ad_sts" is an undefined clock
Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "did:inst3|CLK_OUT" as buffer
Info: Clock "clk" Internal fmax is restricted to 333.33 MHz between source register "adc_1:inst|flag" and destination register "adc_1:inst|flag"
    Info: fmax restricted to Clock High delay (1.5 ns) plus Clock Low delay (1.5 ns) : restricted to 3.0 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.500 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4_H2; Fanout = 2; REG Node = 'adc_1:inst|flag'
            Info: 2: + IC(0.400 ns) + CELL(0.500 ns) = 0.900 ns; Loc. = LC6_H2; Fanout = 1; COMB Node = 'adc_1:inst|always0~0'
            Info: 3: + IC(0.400 ns) + CELL(0.200 ns) = 1.500 ns; Loc. = LC4_H2; Fanout = 2; REG Node = 'adc_1:inst|flag'
            Info: Total cell delay = 0.700 ns ( 46.67 % )
            Info: Total interconnect delay = 0.800 ns ( 53.33 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 3.700 ns
                Info: 1: + IC(0.000 ns) + CELL(0.300 ns) = 0.300 ns; Loc. = PIN_79; Fanout = 4; CLK Node = 'clk'
                Info: 2: + IC(0.800 ns) + CELL(0.600 ns) = 1.700 ns; Loc. = LC1_F26; Fanout = 2; REG Node = 'did:inst3|CLK_OUT'
                Info: 3: + IC(2.000 ns) + CELL(0.000 ns) = 3.700 ns; Loc. = LC4_H2; Fanout = 2; REG Node = 'adc_1:inst|flag'
                Info: Total cell delay = 0.900 ns ( 24.32 % )
                Info: Total interconnect delay = 2.800 ns ( 75.68 % )
            Info: - Longest clock path from clock "clk" to source register is 3.700 ns
                Info: 1: + IC(0.000 ns) + CELL(0.300 ns) = 0.300 ns; Loc. = PIN_79; Fanout = 4; CLK Node = 'clk'
                Info: 2: + IC(0.800 ns) + CELL(0.600 ns) = 1.700 ns; Loc. = LC1_F26; Fanout = 2; REG Node = 'did:inst3|CLK_OUT'
                Info: 3: + IC(2.000 ns) + CELL(0.000 ns) = 3.700 ns; Loc. = LC4_H2; Fanout = 2; REG Node = 'adc_1:inst|flag'
                Info: Total cell delay = 0.900 ns ( 24.32 % )
                Info: Total interconnect delay = 2.800 ns ( 75.68 % )
        Info: + Micro clock to output delay of source is 0.600 ns
        Info: + Micro setup delay of destination is 0.400 ns
Info: Clock "ad_sts" Internal fmax is restricted to 333.33 MHz between source register "adc_4:inst11|f_r" and destination register "adc_4:inst11|f_r"
    Info: fmax restricted to Clock High delay (1.5 ns) plus Clock Low delay (1.5 ns) : restricted to 3.0 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 0.500 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3_H2; Fanout = 4; REG Node = 'adc_4:inst11|f_r'
            Info: 2: + IC(0.400 ns) + CELL(0.100 ns) = 0.500 ns; Loc. = LC3_H2; Fanout = 4; REG Node = 'adc_4:inst11|f_r'
            Info: Total cell delay = 0.100 ns ( 20.00 % )
            Info: Total interconnect delay = 0.400 ns ( 80.00 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "ad_sts" to destination register is 3.500 ns
                Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_103; Fanout = 13; CLK Node = 'ad_sts'
                Info: 2: + IC(1.500 ns) + CELL(0.000 ns) = 3.500 ns; Loc. = LC3_H2; Fanout = 4; REG Node = 'adc_4:inst11|f_r'
                Info: Total cell delay = 2.000 ns ( 57.14 % )
                Info: Total interconnect delay = 1.500 ns ( 42.86 % )
            Info: - Longest clock path from clock "ad_sts" to source register is 3.500 ns
                Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_103; Fanout = 13; CLK Node = 'ad_sts'
                Info: 2: + IC(1.500 ns) + CELL(0.000 ns) = 3.500 ns; Loc. = LC3_H2; Fanout = 4; REG Node = 'adc_4:inst11|f_r'
                Info: Total cell delay = 2.000 ns ( 57.14 % )
                Info: Total interconnect delay = 1.500 ns ( 42.86 % )
        Info: + Micro clock to output delay of source is 0.600 ns
        Info: + Micro setup delay of destination is 0.400 ns
Info: tsu for register "adc_3:inst10|data_out[2]" (data pin = "data_in[2]", clock pin = "ad_sts") is 0.900 ns
    Info: + Longest pin to register delay is 4.000 ns
        Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_92; Fanout = 1; PIN Node = 'data_in[2]'
        Info: 2: + IC(1.900 ns) + CELL(0.100 ns) = 4.000 ns; Loc. = LC5_H2; Fanout = 1; REG Node = 'adc_3:inst10|data_out[2]'
        Info: Total cell delay = 2.100 ns ( 52.50 % )
        Info: Total interconnect delay = 1.900 ns ( 47.50 % )
    Info: + Micro setup delay of destination is 0.400 ns
    Info: - Shortest clock path from clock "ad_sts" to destination register is 3.500 ns
        Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_103; Fanout = 13; CLK Node = 'ad_sts'
        Info: 2: + IC(1.500 ns) + CELL(0.000 ns) = 3.500 ns; Loc. = LC5_H2; Fanout = 1; REG Node = 'adc_3:inst10|data_out[2]'
        Info: Total cell delay = 2.000 ns ( 57.14 % )
        Info: Total interconnect delay = 1.500 ns ( 42.86 % )
Info: tco from clock "ad_sts" to destination pin "data_out1[0]" through register "adc_3:inst10|data_out[0]" is 11.400 ns
    Info: + Longest clock path from clock "ad_sts" to source register is 4.300 ns
        Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_103; Fanout = 13; CLK Node = 'ad_sts'
        Info: 2: + IC(2.300 ns) + CELL(0.000 ns) = 4.300 ns; Loc. = LC7_D12; Fanout = 1; REG Node = 'adc_3:inst10|data_out[0]'
        Info: Total cell delay = 2.000 ns ( 46.51 % )
        Info: Total interconnect delay = 2.300 ns ( 53.49 % )
    Info: + Micro clock to output delay of source is 0.600 ns
    Info: + Longest register to pin delay is 6.500 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC7_D12; Fanout = 1; REG Node = 'adc_3:inst10|data_out[0]'
        Info: 2: + IC(2.300 ns) + CELL(4.200 ns) = 6.500 ns; Loc. = PIN_47; Fanout = 0; PIN Node = 'data_out1[0]'
        Info: Total cell delay = 4.200 ns ( 64.62 % )
        Info: Total interconnect delay = 2.300 ns ( 35.38 % )
Info: th for register "adc_3:inst10|data_out[1]" (data pin = "data_in[1]", clock pin = "ad_sts") is 1.100 ns
    Info: + Longest clock path from clock "ad_sts" to destination register is 4.300 ns
        Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_103; Fanout = 13; CLK Node = 'ad_sts'
        Info: 2: + IC(2.300 ns) + CELL(0.000 ns) = 4.300 ns; Loc. = LC2_D12; Fanout = 1; REG Node = 'adc_3:inst10|data_out[1]'
        Info: Total cell delay = 2.000 ns ( 46.51 % )
        Info: Total interconnect delay = 2.300 ns ( 53.49 % )
    Info: + Micro hold delay of destination is 0.500 ns
    Info: - Shortest pin to register delay is 3.700 ns
        Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_90; Fanout = 1; PIN Node = 'data_in[1]'
        Info: 2: + IC(1.600 ns) + CELL(0.100 ns) = 3.700 ns; Loc. = LC2_D12; Fanout = 1; REG Node = 'adc_3:inst10|data_out[1]'
        Info: Total cell delay = 2.100 ns ( 56.76 % )
        Info: Total interconnect delay = 1.600 ns ( 43.24 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Processing ended: Sat Dec 29 11:21:30 2007
    Info: Elapsed time: 00:00:02