adc.vwf

来自「用verilog编程实现的基于FPGA的AD数据采集程序」· VWF 代码 · 共 3,528 行 · 第 1/4 页

VWF
3,528 行
字号
1234

TRANSITION_LIST("data_out4[11]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 100000.0;
	}
}

TRANSITION_LIST("data_out4[10]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 100000.0;
	}
}

TRANSITION_LIST("data_out4[9]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 100000.0;
	}
}

TRANSITION_LIST("data_out4[8]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 100000.0;
	}
}

TRANSITION_LIST("data_out4[7]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 100000.0;
	}
}

TRANSITION_LIST("data_out4[6]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 100000.0;
	}
}

TRANSITION_LIST("data_out4[5]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 100000.0;
	}
}

TRANSITION_LIST("data_out4[4]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 100000.0;
	}
}

TRANSITION_LIST("data_out4[3]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 100000.0;
	}
}

TRANSITION_LIST("data_out4[2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 100000.0;
	}
}

TRANSITION_LIST("data_out4[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 100000.0;
	}
}

TRANSITION_LIST("data_out4[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 100000.0;
	}
}

TRANSITION_LIST("data_out5[11]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 100000.0;
	}
}

TRANSITION_LIST("data_out5[10]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 100000.0;
	}
}

TRANSITION_LIST("data_out5[9]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 100000.0;
	}
}

TRANSITION_LIST("data_out5[8]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 100000.0;
	}
}

TRANSITION_LIST("data_out5[7]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 100000.0;
	}
}

TRANSITION_LIST("data_out5[6]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 100000.0;
	}
}

TRANSITION_LIST("data_out5[5]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 100000.0;
	}
}

TRANSITION_LIST("data_out5[4]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 100000.0;
	}
}

TRANSITION_LIST("data_out5[3]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 100000.0;
	}
}

TRANSITION_LIST("data_out5[2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 100000.0;
	}
}

TRANSITION_LIST("data_out5[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 100000.0;
	}
}

TRANSITION_LIST("data_out5[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 100000.0;
	}
}

TRANSITION_LIST("data_out6[11]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 100000.0;
	}
}

TRANSITION_LIST("data_out6[10]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 100000.0;
	}
}

TRANSITION_LIST("data_out6[9]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 100000.0;
	}
}

TRANSITION_LIST("data_out6[8]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 100000.0;
	}
}

TRANSITION_LIST("data_out6[7]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 100000.0;
	}
}

TRANSITION_LIST("data_out6[6]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 100000.0;
	}
}

TRANSITION_LIST("data_out6[5]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 100000.0;
	}
}

TRANSITION_LIST("data_out6[4]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 100000.0;
	}
}

TRANSITION_LIST("data_out6[3]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 100000.0;
	}
}

TRANSITION_LIST("data_out6[2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 100000.0;
	}
}

TRANSITION_LIST("data_out6[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 100000.0;
	}
}

TRANSITION_LIST("data_out6[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 100000.0;
	}
}

TRANSITION_LIST("data_out7[11]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 100000.0;
	}
}

TRANSITION_LIST("data_out7[10]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 100000.0;
	}
}

TRANSITION_LIST("data_out7[9]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 100000.0;
	}
}

TRANSITION_LIST("data_out7[8]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 100000.0;
	}
}

TRANSITION_LIST("data_out7[7]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 100000.0;
	}
}

TRANSITION_LIST("data_out7[6]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 100000.0;
	}
}

TRANSITION_LIST("data_out7[5]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 100000.0;
	}
}

TRANSITION_LIST("data_out7[4]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 100000.0;
	}
}

TRANSITION_LIST("data_out7[3]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 100000.0;
	}
}

TRANSITION_LIST("data_out7[2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 100000.0;
	}
}

TRANSITION_LIST("data_out7[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 100000.0;
	}
}

TRANSITION_LIST("data_out7[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 100000.0;
	}
}

TRANSITION_LIST("data_out8[11]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 100000.0;
	}
}

TRANSITION_LIST("data_out8[10]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 100000.0;
	}
}

TRANSITION_LIST("data_out8[9]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 100000.0;
	}
}

TRANSITION_LIST("data_out8[8]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 100000.0;
	}
}

TRANSITION_LIST("data_out8[7]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 100000.0;
	}
}

TRANSITION_LIST("data_out8[6]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 100000.0;
	}
}

TRANSITION_LIST("data_out8[5]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 100000.0;
	}
}

TRANSITION_LIST("data_out8[4]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 100000.0;
	}
}

TRANSITION_LIST("data_out8[3]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 100000.0;
	}
}

TRANSITION_LIST("data_out8[2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 100000.0;
	}
}

TRANSITION_LIST("data_out8[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 100000.0;
	}
}

TRANSITION_LIST("data_out8[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 100000.0;
	}
}

TRANSITION_LIST("reset")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 150.0;
		LEVEL 1 FOR 99850.0;
	}
}

DISPLAY_LINE
{
	CHANNEL = "clk";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 0;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "reset";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 1;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "ad_sts";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 2;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "control";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 3;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "data_in";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 4;
	TREE_LEVEL = 0;
	CHILDREN = 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16;
}

DISPLAY_LINE
{
	CHANNEL = "data_in[11]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 5;
	TREE_LEVEL = 1;
	PARENT = 4;
}

DISPLAY_LINE
{
	CHANNEL = "data_in[10]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 6;
	TREE_LEVEL = 1;
	PARENT = 4;
}

DISPLAY_LINE
{
	CHANNEL = "data_in[9]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 7;
	TREE_LEVEL = 1;
	PARENT = 4;
}

DISPLAY_LINE
{
	CHANNEL = "data_in[8]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 8;
	TREE_LEVEL = 1;
	PARENT = 4;
}

DISPLAY_LINE
{
	CHANNEL = "data_in[7]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 9;
	TREE_LEVEL = 1;
	PARENT = 4;
}

DISPLAY_LINE
{
	CHANNEL = "data_in[6]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 10;
	TREE_LEVEL = 1;
	PARENT = 4;
}

DISPLAY_LINE
{
	CHANNEL = "data_in[5]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 11;
	TREE_LEVEL = 1;
	PARENT = 4;
}

DISPLAY_LINE
{
	CHANNEL = "data_in[4]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 12;
	TREE_LEVEL = 1;
	PARENT = 4;
}

DISPLAY_LINE
{
	CHANNEL = "data_in[3]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 13;
	TREE_LEVEL = 1;
	PARENT = 4;
}

DISPLAY_LINE
{
	CHANNEL = "data_in[2]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 14;
	TREE_LEVEL = 1;
	PARENT = 4;
}

DISPLAY_LINE
{
	CHANNEL = "data_in[1]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 15;
	TREE_LEVEL = 1;
	PARENT = 4;
}

DISPLAY_LINE
{
	CHANNEL = "data_in[0]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 16;
	TREE_LEVEL = 1;
	PARENT = 4;
}

DISPLAY_LINE
{
	CHANNEL = "data_out1";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 17;
	TREE_LEVEL = 0;
	CHILDREN = 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29;
}

DISPLAY_LINE
{
	CHANNEL = "data_out1[11]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 18;
	TREE_LEVEL = 1;
	PARENT = 17;
}

DISPLAY_LINE
{
	CHANNEL = "data_out1[10]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 19;
	TREE_LEVEL = 1;
	PARENT = 17;
}

DISPLAY_LINE
{
	CHANNEL = "data_out1[9]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 20;
	TREE_LEVEL = 1;
	PARENT = 17;
}

DISPLAY_LINE
{
	CHANNEL = "data_out1[8]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 21;
	TREE_LEVEL = 1;
	PARENT = 17;
}

DISPLAY_LINE
{
	CHANNEL = "data_out1[7]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 22;
	TREE_LEVEL = 1;
	PARENT = 17;
}

DISPLAY_LINE
{
	CHANNEL = "data_out1[6]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 23;
	TREE_LEVEL = 1;
	PARENT = 17;
}

DISPLAY_LINE
{
	CHANNEL = "data_out1[5]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 24;
	TREE_LEVEL = 1;
	PARENT = 17;
}

DISPLAY_LINE
{
	CHANNEL = "data_out1[4]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 25;
	TREE_LEVEL = 1;
	PARENT = 17;
}

DISPLAY_LINE
{
	CHANNEL = "data_out1[3]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 26;
	TREE_LEVEL = 1;
	PARENT = 17;
}

DISPLAY_LINE
{
	CHANNEL = "data_out1[2]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 27;
	TREE_LEVEL = 1;
	PARENT = 17;
}

DISPLAY_LINE
{
	CHANNEL = "data_out1[1]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 28;
	TREE_LEVEL = 1;
	PARENT = 17;
}

DISPLAY_LINE
{
	CHANNEL = "data_out1[0]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 29;
	TREE_LEVEL = 1;
	PARENT = 17;
}

DISPLAY_LINE
{
	CHANNEL = "data_out2";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 30;
	TREE_LEVEL = 0;
	CHILDREN = 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42;
}

DISPLAY_LINE
{
	CHANNEL = "data_out2[11]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 31;
	TREE_LEVEL = 1;
	PARENT = 30;
}

DISPLAY_LINE
{
	CHANNEL = "data_out2[10]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 32;
	TREE_LEVEL = 1;
	PARENT = 30;
}

DISPLAY_LINE
{
	CHANNEL = "data_out2[9]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
1234

adc.vwf - 源码说明

本页面展示了「用verilog编程实现的基于FPGA的AD数据采集程序」中的 adc.vwf 源码文件，采用 VWF 编程语言编写，共 3,528 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。

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