adc.fit.summary

来自「用verilog编程实现的基于FPGA的AD数据采集程序」· SUMMARY 代码 · 共 13 行

Flow Status : Successful - Sat Dec 29 11:21:22 2007
Quartus II Version : 5.0 Build 171 11/03/2005 SP 2 SJ Full Version
Revision Name : adc
Top-level Entity Name : adc
Family : ACEX1K
Device : EP1K100QC208-1
Timing Models : Final
Met timing requirements : N/A
Total logic elements : 20 / 4,992 ( < 1 % )
Total pins : 114 / 147 ( 77 % )
Total memory bits : 0 / 49,152 ( 0 % )
Total PLLs : 0 / 1 ( 0 % )