📄 adc_4.tan.rpt
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Timing Analyzer report for adc_4
Thu Dec 06 19:47:59 2007
Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Clock Settings Summary
5. Clock Setup: 'ad_sts'
6. tsu
7. tco
8. th
9. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+------------------------------------------------+----------+----------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+------------------------------------------------+----------+----------+------------+----------+--------------+
; Worst-case tsu ; N/A ; None ; 1.500 ns ; reset ; f_r~reg0 ; ; ad_sts ; 0 ;
; Worst-case tco ; N/A ; None ; 6.300 ns ; f_r~reg0 ; f_r ; ad_sts ; ; 0 ;
; Worst-case th ; N/A ; None ; -0.600 ns ; reset ; f_r~reg0 ; ; ad_sts ; 0 ;
; Clock Setup: 'ad_sts' ; N/A ; None ; Restricted to 333.33 MHz ( period = 3.000 ns ) ; f_r~reg0 ; f_r~reg0 ; ad_sts ; ad_sts ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+------------------------------------------------+----------+----------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP1K100QC208-1 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same as Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; Off ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; ad_sts ; ; User Pin ; NONE ; 0.000 ns ; 0.000 ns ; NONE ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'ad_sts' ;
+-------+------------------------------------------------+----------+----------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+----------+----------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; Restricted to 333.33 MHz ( period = 3.000 ns ) ; f_r~reg0 ; f_r~reg0 ; ad_sts ; ad_sts ; None ; None ; 0.500 ns ;
+-------+------------------------------------------------+----------+----------+------------+----------+-----------------------------+---------------------------+-------------------------+
+-----------------------------------------------------------------+
; tsu ;
+-------+--------------+------------+-------+----------+----------+
; Slack ; Required tsu ; Actual tsu ; From ; To ; To Clock ;
+-------+--------------+------------+-------+----------+----------+
; N/A ; None ; 1.500 ns ; reset ; f_r~reg0 ; ad_sts ;
+-------+--------------+------------+-------+----------+----------+
+-----------------------------------------------------------------+
; tco ;
+-------+--------------+------------+----------+-----+------------+
; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
+-------+--------------+------------+----------+-----+------------+
; N/A ; None ; 6.300 ns ; f_r~reg0 ; f_r ; ad_sts ;
+-------+--------------+------------+----------+-----+------------+
+-----------------------------------------------------------------------+
; th ;
+---------------+-------------+-----------+-------+----------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To ; To Clock ;
+---------------+-------------+-----------+-------+----------+----------+
; N/A ; None ; -0.600 ns ; reset ; f_r~reg0 ; ad_sts ;
+---------------+-------------+-----------+-------+----------+----------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version
Info: Processing started: Thu Dec 06 19:47:57 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off adc_4 -c adc_4
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "ad_sts" is an undefined clock
Info: Clock "ad_sts" Internal fmax is restricted to 333.33 MHz between source register "f_r~reg0" and destination register "f_r~reg0"
Info: fmax restricted to Clock High delay (1.5 ns) plus Clock Low delay (1.5 ns) : restricted to 3.0 ns. Expand message to see actual delay path.
Info: + Longest register to register delay is 0.500 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2_C25; Fanout = 2; REG Node = 'f_r~reg0'
Info: 2: + IC(0.400 ns) + CELL(0.100 ns) = 0.500 ns; Loc. = LC2_C25; Fanout = 2; REG Node = 'f_r~reg0'
Info: Total cell delay = 0.100 ns ( 20.00 % )
Info: Total interconnect delay = 0.400 ns ( 80.00 % )
Info: - Smallest clock skew is 0.000 ns
Info: + Shortest clock path from clock "ad_sts" to destination register is 1.100 ns
Info: 1: + IC(0.000 ns) + CELL(0.300 ns) = 0.300 ns; Loc. = PIN_79; Fanout = 1; CLK Node = 'ad_sts'
Info: 2: + IC(0.800 ns) + CELL(0.000 ns) = 1.100 ns; Loc. = LC2_C25; Fanout = 2; REG Node = 'f_r~reg0'
Info: Total cell delay = 0.300 ns ( 27.27 % )
Info: Total interconnect delay = 0.800 ns ( 72.73 % )
Info: - Longest clock path from clock "ad_sts" to source register is 1.100 ns
Info: 1: + IC(0.000 ns) + CELL(0.300 ns) = 0.300 ns; Loc. = PIN_79; Fanout = 1; CLK Node = 'ad_sts'
Info: 2: + IC(0.800 ns) + CELL(0.000 ns) = 1.100 ns; Loc. = LC2_C25; Fanout = 2; REG Node = 'f_r~reg0'
Info: Total cell delay = 0.300 ns ( 27.27 % )
Info: Total interconnect delay = 0.800 ns ( 72.73 % )
Info: + Micro clock to output delay of source is 0.600 ns
Info: + Micro setup delay of destination is 0.400 ns
Info: tsu for register "f_r~reg0" (data pin = "reset", clock pin = "ad_sts") is 1.500 ns
Info: + Longest pin to register delay is 2.200 ns
Info: 1: + IC(0.000 ns) + CELL(0.300 ns) = 0.300 ns; Loc. = PIN_184; Fanout = 1; PIN Node = 'reset'
Info: 2: + IC(1.700 ns) + CELL(0.200 ns) = 2.200 ns; Loc. = LC2_C25; Fanout = 2; REG Node = 'f_r~reg0'
Info: Total cell delay = 0.500 ns ( 22.73 % )
Info: Total interconnect delay = 1.700 ns ( 77.27 % )
Info: + Micro setup delay of destination is 0.400 ns
Info: - Shortest clock path from clock "ad_sts" to destination register is 1.100 ns
Info: 1: + IC(0.000 ns) + CELL(0.300 ns) = 0.300 ns; Loc. = PIN_79; Fanout = 1; CLK Node = 'ad_sts'
Info: 2: + IC(0.800 ns) + CELL(0.000 ns) = 1.100 ns; Loc. = LC2_C25; Fanout = 2; REG Node = 'f_r~reg0'
Info: Total cell delay = 0.300 ns ( 27.27 % )
Info: Total interconnect delay = 0.800 ns ( 72.73 % )
Info: tco from clock "ad_sts" to destination pin "f_r" through register "f_r~reg0" is 6.300 ns
Info: + Longest clock path from clock "ad_sts" to source register is 1.100 ns
Info: 1: + IC(0.000 ns) + CELL(0.300 ns) = 0.300 ns; Loc. = PIN_79; Fanout = 1; CLK Node = 'ad_sts'
Info: 2: + IC(0.800 ns) + CELL(0.000 ns) = 1.100 ns; Loc. = LC2_C25; Fanout = 2; REG Node = 'f_r~reg0'
Info: Total cell delay = 0.300 ns ( 27.27 % )
Info: Total interconnect delay = 0.800 ns ( 72.73 % )
Info: + Micro clock to output delay of source is 0.600 ns
Info: + Longest register to pin delay is 4.600 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2_C25; Fanout = 2; REG Node = 'f_r~reg0'
Info: 2: + IC(0.400 ns) + CELL(4.200 ns) = 4.600 ns; Loc. = PIN_140; Fanout = 0; PIN Node = 'f_r'
Info: Total cell delay = 4.200 ns ( 91.30 % )
Info: Total interconnect delay = 0.400 ns ( 8.70 % )
Info: th for register "f_r~reg0" (data pin = "reset", clock pin = "ad_sts") is -0.600 ns
Info: + Longest clock path from clock "ad_sts" to destination register is 1.100 ns
Info: 1: + IC(0.000 ns) + CELL(0.300 ns) = 0.300 ns; Loc. = PIN_79; Fanout = 1; CLK Node = 'ad_sts'
Info: 2: + IC(0.800 ns) + CELL(0.000 ns) = 1.100 ns; Loc. = LC2_C25; Fanout = 2; REG Node = 'f_r~reg0'
Info: Total cell delay = 0.300 ns ( 27.27 % )
Info: Total interconnect delay = 0.800 ns ( 72.73 % )
Info: + Micro hold delay of destination is 0.500 ns
Info: - Shortest pin to register delay is 2.200 ns
Info: 1: + IC(0.000 ns) + CELL(0.300 ns) = 0.300 ns; Loc. = PIN_184; Fanout = 1; PIN Node = 'reset'
Info: 2: + IC(1.700 ns) + CELL(0.200 ns) = 2.200 ns; Loc. = LC2_C25; Fanout = 2; REG Node = 'f_r~reg0'
Info: Total cell delay = 0.500 ns ( 22.73 % )
Info: Total interconnect delay = 1.700 ns ( 77.27 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
Info: Processing ended: Thu Dec 06 19:47:59 2007
Info: Elapsed time: 00:00:02
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