📄 adc_1.tan.qmsg

📁 用verilog编程实现的基于FPGA的AD数据采集程序
💻 QMSG
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{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register add\[0\]~reg0 register flag 294.12 MHz 3.4 ns Internal " "Info: Clock \"clk\" has Internal fmax of 294.12 MHz between source register \"add\[0\]~reg0\" and destination register \"flag\" (period= 3.4 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.400 ns + Longest register register " "Info: + Longest register to register delay is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns add\[0\]~reg0 1 REG LC4_B33 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4_B33; Fanout = 5; REG Node = 'add\[0\]~reg0'" {  } { { "F:/adc_1/db/adc_1_cmp.qrpt" "" { Report "F:/adc_1/db/adc_1_cmp.qrpt" Compiler "adc_1" "UNKNOWN" "V1" "F:/adc_1/db/adc_1.quartus_db" { Floorplan "F:/adc_1/" "" "" { add[0]~reg0 } "NODE_NAME" } "" } } { "adc_1.v" "" { Text "F:/adc_1/adc_1.v" 47 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.800 ns) + CELL(0.700 ns) 1.500 ns flag~225 2 COMB LC2_B34 1 " "Info: 2: + IC(0.800 ns) + CELL(0.700 ns) = 1.500 ns; Loc. = LC2_B34; Fanout = 1; COMB Node = 'flag~225'" {  } { { "F:/adc_1/db/adc_1_cmp.qrpt" "" { Report "F:/adc_1/db/adc_1_cmp.qrpt" Compiler "adc_1" "UNKNOWN" "V1" "F:/adc_1/db/adc_1.quartus_db" { Floorplan "F:/adc_1/" "" "1.500 ns" { add[0]~reg0 flag~225 } "NODE_NAME" } "" } } { "adc_1.v" "" { Text "F:/adc_1/adc_1.v" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.800 ns) + CELL(0.100 ns) 2.400 ns flag 3 REG LC1_B33 4 " "Info: 3: + IC(0.800 ns) + CELL(0.100 ns) = 2.400 ns; Loc. = LC1_B33; Fanout = 4; REG Node = 'flag'" {  } { { "F:/adc_1/db/adc_1_cmp.qrpt" "" { Report "F:/adc_1/db/adc_1_cmp.qrpt" Compiler "adc_1" "UNKNOWN" "V1" "F:/adc_1/db/adc_1.quartus_db" { Floorplan "F:/adc_1/" "" "0.900 ns" { flag~225 flag } "NODE_NAME" } "" } } { "adc_1.v" "" { Text "F:/adc_1/adc_1.v" 6 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.800 ns 33.33 % " "Info: Total cell delay = 0.800 ns ( 33.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.600 ns 66.67 % " "Info: Total interconnect delay = 1.600 ns ( 66.67 % )" {  } {  } 0}  } { { "F:/adc_1/db/adc_1_cmp.qrpt" "" { Report "F:/adc_1/db/adc_1_cmp.qrpt" Compiler "adc_1" "UNKNOWN" "V1" "F:/adc_1/db/adc_1.quartus_db" { Floorplan "F:/adc_1/" "" "2.400 ns" { add[0]~reg0 flag~225 flag } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.400 ns" { add[0]~reg0 flag~225 flag } { 0.000ns 0.800ns 0.800ns } { 0.000ns 0.700ns 0.100ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 1.100 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 1.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 0.300 ns clk 1 CLK PIN_79 6 " "Info: 1: + IC(0.000 ns) + CELL(0.300 ns) = 0.300 ns; Loc. = PIN_79; Fanout = 6; CLK Node = 'clk'" {  } { { "F:/adc_1/db/adc_1_cmp.qrpt" "" { Report "F:/adc_1/db/adc_1_cmp.qrpt" Compiler "adc_1" "UNKNOWN" "V1" "F:/adc_1/db/adc_1.quartus_db" { Floorplan "F:/adc_1/" "" "" { clk } "NODE_NAME" } "" } } { "adc_1.v" "" { Text "F:/adc_1/adc_1.v" 2 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.800 ns) + CELL(0.000 ns) 1.100 ns flag 2 REG LC1_B33 4 " "Info: 2: + IC(0.800 ns) + CELL(0.000 ns) = 1.100 ns; Loc. = LC1_B33; Fanout = 4; REG Node = 'flag'" {  } { { "F:/adc_1/db/adc_1_cmp.qrpt" "" { Report "F:/adc_1/db/adc_1_cmp.qrpt" Compiler "adc_1" "UNKNOWN" "V1" "F:/adc_1/db/adc_1.quartus_db" { Floorplan "F:/adc_1/" "" "0.800 ns" { clk flag } "NODE_NAME" } "" } } { "adc_1.v" "" { Text "F:/adc_1/adc_1.v" 6 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.300 ns 27.27 % " "Info: Total cell delay = 0.300 ns ( 27.27 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.800 ns 72.73 % " "Info: Total interconnect delay = 0.800 ns ( 72.73 % )" {  } {  } 0}  } { { "F:/adc_1/db/adc_1_cmp.qrpt" "" { Report "F:/adc_1/db/adc_1_cmp.qrpt" Compiler "adc_1" "UNKNOWN" "V1" "F:/adc_1/db/adc_1.quartus_db" { Floorplan "F:/adc_1/" "" "1.100 ns" { clk flag } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "1.100 ns" { clk clk~out flag } { 0.000ns 0.000ns 0.800ns } { 0.000ns 0.300ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 1.100 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 1.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 0.300 ns clk 1 CLK PIN_79 6 " "Info: 1: + IC(0.000 ns) + CELL(0.300 ns) = 0.300 ns; Loc. = PIN_79; Fanout = 6; CLK Node = 'clk'" {  } { { "F:/adc_1/db/adc_1_cmp.qrpt" "" { Report "F:/adc_1/db/adc_1_cmp.qrpt" Compiler "adc_1" "UNKNOWN" "V1" "F:/adc_1/db/adc_1.quartus_db" { Floorplan "F:/adc_1/" "" "" { clk } "NODE_NAME" } "" } } { "adc_1.v" "" { Text "F:/adc_1/adc_1.v" 2 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.800 ns) + CELL(0.000 ns) 1.100 ns add\[0\]~reg0 2 REG LC4_B33 5 " "Info: 2: + IC(0.800 ns) + CELL(0.000 ns) = 1.100 ns; Loc. = LC4_B33; Fanout = 5; REG Node = 'add\[0\]~reg0'" {  } { { "F:/adc_1/db/adc_1_cmp.qrpt" "" { Report "F:/adc_1/db/adc_1_cmp.qrpt" Compiler "adc_1" "UNKNOWN" "V1" "F:/adc_1/db/adc_1.quartus_db" { Floorplan "F:/adc_1/" "" "0.800 ns" { clk add[0]~reg0 } "NODE_NAME" } "" } } { "adc_1.v" "" { Text "F:/adc_1/adc_1.v" 47 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.300 ns 27.27 % " "Info: Total cell delay = 0.300 ns ( 27.27 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.800 ns 72.73 % " "Info: Total interconnect delay = 0.800 ns ( 72.73 % )" {  } {  } 0}  } { { "F:/adc_1/db/adc_1_cmp.qrpt" "" { Report "F:/adc_1/db/adc_1_cmp.qrpt" Compiler "adc_1" "UNKNOWN" "V1" "F:/adc_1/db/adc_1.quartus_db" { Floorplan "F:/adc_1/" "" "1.100 ns" { clk add[0]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "1.100 ns" { clk clk~out add[0]~reg0 } { 0.000ns 0.000ns 0.800ns } { 0.000ns 0.300ns 0.000ns } } }  } 0}  } { { "F:/adc_1/db/adc_1_cmp.qrpt" "" { Report "F:/adc_1/db/adc_1_cmp.qrpt" Compiler "adc_1" "UNKNOWN" "V1" "F:/adc_1/db/adc_1.quartus_db" { Floorplan "F:/adc_1/" "" "1.100 ns" { clk flag } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "1.100 ns" { clk clk~out flag } { 0.000ns 0.000ns 0.800ns } { 0.000ns 0.300ns 0.000ns } } } { "F:/adc_1/db/adc_1_cmp.qrpt" "" { Report "F:/adc_1/db/adc_1_cmp.qrpt" Compiler "adc_1" "UNKNOWN" "V1" "F:/adc_1/db/adc_1.quartus_db" { Floorplan "F:/adc_1/" "" "1.100 ns" { clk add[0]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "1.100 ns" { clk clk~out add[0]~reg0 } { 0.000ns 0.000ns 0.800ns } { 0.000ns 0.300ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.600 ns + " "Info: + Micro clock to output delay of source is 0.600 ns" {  } { { "adc_1.v" "" { Text "F:/adc_1/adc_1.v" 47 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.400 ns + " "Info: + Micro setup delay of destination is 0.400 ns" {  } { { "adc_1.v" "" { Text "F:/adc_1/adc_1.v" 6 -1 0 } }  } 0}  } { { "F:/adc_1/db/adc_1_cmp.qrpt" "" { Report "F:/adc_1/db/adc_1_cmp.qrpt" Compiler "adc_1" "UNKNOWN" "V1" "F:/adc_1/db/adc_1.quartus_db" { Floorplan "F:/adc_1/" "" "2.400 ns" { add[0]~reg0 flag~225 flag } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.400 ns" { add[0]~reg0 flag~225 flag } { 0.000ns 0.800ns 0.800ns } { 0.000ns 0.700ns 0.100ns } } } { "F:/adc_1/db/adc_1_cmp.qrpt" "" { Report "F:/adc_1/db/adc_1_cmp.qrpt" Compiler "adc_1" "UNKNOWN" "V1" "F:/adc_1/db/adc_1.quartus_db" { Floorplan "F:/adc_1/" "" "1.100 ns" { clk flag } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "1.100 ns" { clk clk~out flag } { 0.000ns 0.000ns 0.800ns } { 0.000ns 0.300ns 0.000ns } } } { "F:/adc_1/db/adc_1_cmp.qrpt" "" { Report "F:/adc_1/db/adc_1_cmp.qrpt" Compiler "adc_1" "UNKNOWN" "V1" "F:/adc_1/db/adc_1.quartus_db" { Floorplan "F:/adc_1/" "" "1.100 ns" { clk add[0]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "1.100 ns" { clk clk~out add[0]~reg0 } { 0.000ns 0.000ns 0.800ns } { 0.000ns 0.300ns 0.000ns } } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "add\[0\]~reg0 reset clk 3.300 ns register " "Info: tsu for register \"add\[0\]~reg0\" (data pin = \"reset\", clock pin = \"clk\") is 3.300 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.000 ns + Longest pin register " "Info: + Longest pin to register delay is 4.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 0.300 ns reset 1 PIN PIN_184 5 " "Info: 1: + IC(0.000 ns) + CELL(0.300 ns) = 0.300 ns; Loc. = PIN_184; Fanout = 5; PIN Node = 'reset'" {  } { { "F:/adc_1/db/adc_1_cmp.qrpt" "" { Report "F:/adc_1/db/adc_1_cmp.qrpt" Compiler "adc_1" "UNKNOWN" "V1" "F:/adc_1/db/adc_1.quartus_db" { Floorplan "F:/adc_1/" "" "" { reset } "NODE_NAME" } "" } } { "adc_1.v" "" { Text "F:/adc_1/adc_1.v" 2 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.500 ns) 2.800 ns add~331 2 COMB LC6_B34 2 " "Info: 2: + IC(2.000 ns) + CELL(0.500 ns) = 2.800 ns; Loc. = LC6_B34; Fanout = 2; COMB Node = 'add~331'" {  } { { "F:/adc_1/db/adc_1_cmp.qrpt" "" { Report "F:/adc_1/db/adc_1_cmp.qrpt" Compiler "adc_1" "UNKNOWN" "V1" "F:/adc_1/db/adc_1.quartus_db" { Floorplan "F:/adc_1/" "" "2.500 ns" { reset add~331 } "NODE_NAME" } "" } } { "adc_1.v" "" { Text "F:/adc_1/adc_1.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.800 ns) + CELL(0.400 ns) 4.000 ns add\[0\]~reg0 3 REG LC4_B33 5 " "Info: 3: + IC(0.800 ns) + CELL(0.400 ns) = 4.000 ns; Loc. = LC4_B33; Fanout = 5; REG Node = 'add\[0\]~reg0'" {  } { { "F:/adc_1/db/adc_1_cmp.qrpt" "" { Report "F:/adc_1/db/adc_1_cmp.qrpt" Compiler "adc_1" "UNKNOWN" "V1" "F:/adc_1/db/adc_1.quartus_db" { Floorplan "F:/adc_1/" "" "1.200 ns" { add~331 add[0]~reg0 } "NODE_NAME" } "" } } { "adc_1.v" "" { Text "F:/adc_1/adc_1.v" 47 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.200 ns 30.00 % " "Info: Total cell delay = 1.200 ns ( 30.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.800 ns 70.00 % " "Info: Total interconnect delay = 2.800 ns ( 70.00 % )" {  } {  } 0}  } { { "F:/adc_1/db/adc_1_cmp.qrpt" "" { Report "F:/adc_1/db/adc_1_cmp.qrpt" Compiler "adc_1" "UNKNOWN" "V1" "F:/adc_1/db/adc_1.quartus_db" { Floorplan "F:/adc_1/" "" "4.000 ns" { reset add~331 add[0]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "4.000 ns" { reset reset~out add~331 add[0]~reg0 } { 0.000ns 0.000ns 2.000ns 0.800ns } { 0.000ns 0.300ns 0.500ns 0.400ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.400 ns + " "Info: + Micro setup delay of destination is 0.400 ns" {  } { { "adc_1.v" "" { Text "F:/adc_1/adc_1.v" 47 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 1.100 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 1.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 0.300 ns clk 1 CLK PIN_79 6 " "Info: 1: + IC(0.000 ns) + CELL(0.300 ns) = 0.300 ns; Loc. = PIN_79; Fanout = 6; CLK Node = 'clk'" {  } { { "F:/adc_1/db/adc_1_cmp.qrpt" "" { Report "F:/adc_1/db/adc_1_cmp.qrpt" Compiler "adc_1" "UNKNOWN" "V1" "F:/adc_1/db/adc_1.quartus_db" { Floorplan "F:/adc_1/" "" "" { clk } "NODE_NAME" } "" } } { "adc_1.v" "" { Text "F:/adc_1/adc_1.v" 2 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.800 ns) + CELL(0.000 ns) 1.100 ns add\[0\]~reg0 2 REG LC4_B33 5 " "Info: 2: + IC(0.800 ns) + CELL(0.000 ns) = 1.100 ns; Loc. = LC4_B33; Fanout = 5; REG Node = 'add\[0\]~reg0'" {  } { { "F:/adc_1/db/adc_1_cmp.qrpt" "" { Report "F:/adc_1/db/adc_1_cmp.qrpt" Compiler "adc_1" "UNKNOWN" "V1" "F:/adc_1/db/adc_1.quartus_db" { Floorplan "F:/adc_1/" "" "0.800 ns" { clk add[0]~reg0 } "NODE_NAME" } "" } } { "adc_1.v" "" { Text "F:/adc_1/adc_1.v" 47 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.300 ns 27.27 % " "Info: Total cell delay = 0.300 ns ( 27.27 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.800 ns 72.73 % " "Info: Total interconnect delay = 0.800 ns ( 72.73 % )" {  } {  } 0}  } { { "F:/adc_1/db/adc_1_cmp.qrpt" "" { Report "F:/adc_1/db/adc_1_cmp.qrpt" Compiler "adc_1" "UNKNOWN" "V1" "F:/adc_1/db/adc_1.quartus_db" { Floorplan "F:/adc_1/" "" "1.100 ns" { clk add[0]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "1.100 ns" { clk clk~out add[0]~reg0 } { 0.000ns 0.000ns 0.800ns } { 0.000ns 0.300ns 0.000ns } } }  } 0}  } { { "F:/adc_1/db/adc_1_cmp.qrpt" "" { Report "F:/adc_1/db/adc_1_cmp.qrpt" Compiler "adc_1" "UNKNOWN" "V1" "F:/adc_1/db/adc_1.quartus_db" { Floorplan "F:/adc_1/" "" "4.000 ns" { reset add~331 add[0]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "4.000 ns" { reset reset~out add~331 add[0]~reg0 } { 0.000ns 0.000ns 2.000ns 0.800ns } { 0.000ns 0.300ns 0.500ns 0.400ns } } } { "F:/adc_1/db/adc_1_cmp.qrpt" "" { Report "F:/adc_1/db/adc_1_cmp.qrpt" Compiler "adc_1" "UNKNOWN" "V1" "F:/adc_1/db/adc_1.quartus_db" { Floorplan "F:/adc_1/" "" "1.100 ns" { clk add[0]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "1.100 ns" { clk clk~out add[0]~reg0 } { 0.000ns 0.000ns 0.800ns } { 0.000ns 0.300ns 0.000ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk add\[0\] add\[0\]~reg0 6.900 ns register " "Info: tco from clock \"clk\" to destination pin \"add\[0\]\" through register \"add\[0\]~reg0\" is 6.900 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 1.100 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 1.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 0.300 ns clk 1 CLK PIN_79 6 " "Info: 1: + IC(0.000 ns) + CELL(0.300 ns) = 0.300 ns; Loc. = PIN_79; Fanout = 6; CLK Node = 'clk'" {  } { { "F:/adc_1/db/adc_1_cmp.qrpt" "" { Report "F:/adc_1/db/adc_1_cmp.qrpt" Compiler "adc_1" "UNKNOWN" "V1" "F:/adc_1/db/adc_1.quartus_db" { Floorplan "F:/adc_1/" "" "" { clk } "NODE_NAME" } "" } } { "adc_1.v" "" { Text "F:/adc_1/adc_1.v" 2 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.800 ns) + CELL(0.000 ns) 1.100 ns add\[0\]~reg0 2 REG LC4_B33 5 " "Info: 2: + IC(0.800 ns) + CELL(0.000 ns) = 1.100 ns; Loc. = LC4_B33; Fanout = 5; REG Node = 'add\[0\]~reg0'" {  } { { "F:/adc_1/db/adc_1_cmp.qrpt" "" { Report "F:/adc_1/db/adc_1_cmp.qrpt" Compiler "adc_1" "UNKNOWN" "V1" "F:/adc_1/db/adc_1.quartus_db" { Floorplan "F:/adc_1/" "" "0.800 ns" { clk add[0]~reg0 } "NODE_NAME" } "" } } { "adc_1.v" "" { Text "F:/adc_1/adc_1.v" 47 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.300 ns 27.27 % " "Info: Total cell delay = 0.300 ns ( 27.27 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.800 ns 72.73 % " "Info: Total interconnect delay = 0.800 ns ( 72.73 % )" {  } {  } 0}  } { { "F:/adc_1/db/adc_1_cmp.qrpt" "" { Report "F:/adc_1/db/adc_1_cmp.qrpt" Compiler "adc_1" "UNKNOWN" "V1" "F:/adc_1/db/adc_1.quartus_db" { Floorplan "F:/adc_1/" "" "1.100 ns" { clk add[0]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "1.100 ns" { clk clk~out add[0]~reg0 } { 0.000ns 0.000ns 0.800ns } { 0.000ns 0.300ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.600 ns + " "Info: + Micro clock to output delay of source is 0.600 ns" {  } { { "adc_1.v" "" { Text "F:/adc_1/adc_1.v" 47 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.200 ns + Longest register pin " "Info: + Longest register to pin delay is 5.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns add\[0\]~reg0 1 REG LC4_B33 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4_B33; Fanout = 5; REG Node = 'add\[0\]~reg0'" {  } { { "F:/adc_1/db/adc_1_cmp.qrpt" "" { Report "F:/adc_1/db/adc_1_cmp.qrpt" Compiler "adc_1" "UNKNOWN" "V1" "F:/adc_1/db/adc_1.quartus_db" { Floorplan "F:/adc_1/" "" "" { add[0]~reg0 } "NODE_NAME" } "" } } { "adc_1.v" "" { Text "F:/adc_1/adc_1.v" 47 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(4.200 ns) 5.200 ns add\[0\] 2 PIN PIN_144 0 " "Info: 2: + IC(1.000 ns) + CELL(4.200 ns) = 5.200 ns; Loc. = PIN_144; Fanout = 0; PIN Node = 'add\[0\]'" {  } { { "F:/adc_1/db/adc_1_cmp.qrpt" "" { Report "F:/adc_1/db/adc_1_cmp.qrpt" Compiler "adc_1" "UNKNOWN" "V1" "F:/adc_1/db/adc_1.quartus_db" { Floorplan "F:/adc_1/" "" "5.200 ns" { add[0]~reg0 add[0] } "NODE_NAME" } "" } } { "adc_1.v" "" { Text "F:/adc_1/adc_1.v" 3 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.200 ns 80.77 % " "Info: Total cell delay = 4.200 ns ( 80.77 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 19.23 % " "Info: Total interconnect delay = 1.000 ns ( 19.23 % )" {  } {  } 0}  } { { "F:/adc_1/db/adc_1_cmp.qrpt" "" { Report "F:/adc_1/db/adc_1_cmp.qrpt" Compiler "adc_1" "UNKNOWN" "V1" "F:/adc_1/db/adc_1.quartus_db" { Floorplan "F:/adc_1/" "" "5.200 ns" { add[0]~reg0 add[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.200 ns" { add[0]~reg0 add[0] } { 0.000ns 1.000ns } { 0.000ns 4.200ns } } }  } 0}  } { { "F:/adc_1/db/adc_1_cmp.qrpt" "" { Report "F:/adc_1/db/adc_1_cmp.qrpt" Compiler "adc_1" "UNKNOWN" "V1" "F:/adc_1/db/adc_1.quartus_db" { Floorplan "F:/adc_1/" "" "1.100 ns" { clk add[0]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "1.100 ns" { clk clk~out add[0]~reg0 } { 0.000ns 0.000ns 0.800ns } { 0.000ns 0.300ns 0.000ns } } } { "F:/adc_1/db/adc_1_cmp.qrpt" "" { Report "F:/adc_1/db/adc_1_cmp.qrpt" Compiler "adc_1" "UNKNOWN" "V1" "F:/adc_1/db/adc_1.quartus_db" { Floorplan "F:/adc_1/" "" "5.200 ns" { add[0]~reg0 add[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.200 ns" { add[0]~reg0 add[0] } { 0.000ns 1.000ns } { 0.000ns 4.200ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "beg reset clk -0.800 ns register " "Info: th for register \"beg\" (data pin = \"reset\", clock pin = \"clk\") is -0.800 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 1.100 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 1.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 0.300 ns clk 1 CLK PIN_79 6 " "Info: 1: + IC(0.000 ns) + CELL(0.300 ns) = 0.300 ns; Loc. = PIN_79; Fanout = 6; CLK Node = 'clk'" {  } { { "F:/adc_1/db/adc_1_cmp.qrpt" "" { Report "F:/adc_1/db/adc_1_cmp.qrpt" Compiler "adc_1" "UNKNOWN" "V1" "F:/adc_1/db/adc_1.quartus_db" { Floorplan "F:/adc_1/" "" "" { clk } "NODE_NAME" } "" } } { "adc_1.v" "" { Text "F:/adc_1/adc_1.v" 2 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.800 ns) + CELL(0.000 ns) 1.100 ns beg 2 REG LC3_B34 4 " "Info: 2: + IC(0.800 ns) + CELL(0.000 ns) = 1.100 ns; Loc. = LC3_B34; Fanout = 4; REG Node = 'beg'" {  } { { "F:/adc_1/db/adc_1_cmp.qrpt" "" { Report "F:/adc_1/db/adc_1_cmp.qrpt" Compiler "adc_1" "UNKNOWN" "V1" "F:/adc_1/db/adc_1.quartus_db" { Floorplan "F:/adc_1/" "" "0.800 ns" { clk beg } "NODE_NAME" } "" } } { "adc_1.v" "" { Text "F:/adc_1/adc_1.v" 5 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.300 ns 27.27 % " "Info: Total cell delay = 0.300 ns ( 27.27 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.800 ns 72.73 % " "Info: Total interconnect delay = 0.800 ns ( 72.73 % )" {  } {  } 0}  } { { "F:/adc_1/db/adc_1_cmp.qrpt" "" { Report "F:/adc_1/db/adc_1_cmp.qrpt" Compiler "adc_1" "UNKNOWN" "V1" "F:/adc_1/db/adc_1.quartus_db" { Floorplan "F:/adc_1/" "" "1.100 ns" { clk beg } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "1.100 ns" { clk clk~out beg } { 0.000ns 0.000ns 0.800ns } { 0.000ns 0.300ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.500 ns + " "Info: + Micro hold delay of destination is 0.500 ns" {  } { { "adc_1.v" "" { Text "F:/adc_1/adc_1.v" 5 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.400 ns - Shortest pin register " "Info: - Shortest pin to register delay is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 0.300 ns reset 1 PIN PIN_184 5 " "Info: 1: + IC(0.000 ns) + CELL(0.300 ns) = 0.300 ns; Loc. = PIN_184; Fanout = 5; PIN Node = 'reset'" {  } { { "F:/adc_1/db/adc_1_cmp.qrpt" "" { Report "F:/adc_1/db/adc_1_cmp.qrpt" Compiler "adc_1" "UNKNOWN" "V1" "F:/adc_1/db/adc_1.quartus_db" { Floorplan "F:/adc_1/" "" "" { reset } "NODE_NAME" } "" } } { "adc_1.v" "" { Text "F:/adc_1/adc_1.v" 2 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.100 ns) 2.400 ns beg 2 REG LC3_B34 4 " "Info: 2: + IC(2.000 ns) + CELL(0.100 ns) = 2.400 ns; Loc. = LC3_B34; Fanout = 4; REG Node = 'beg'" {  } { { "F:/adc_1/db/adc_1_cmp.qrpt" "" { Report "F:/adc_1/db/adc_1_cmp.qrpt" Compiler "adc_1" "UNKNOWN" "V1" "F:/adc_1/db/adc_1.quartus_db" { Floorplan "F:/adc_1/" "" "2.100 ns" { reset beg } "NODE_NAME" } "" } } { "adc_1.v" "" { Text "F:/adc_1/adc_1.v" 5 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.400 ns 16.67 % " "Info: Total cell delay = 0.400 ns ( 16.67 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 83.33 % " "Info: Total interconnect delay = 2.000 ns ( 83.33 % )" {  } {  } 0}  } { { "F:/adc_1/db/adc_1_cmp.qrpt" "" { Report "F:/adc_1/db/adc_1_cmp.qrpt" Compiler "adc_1" "UNKNOWN" "V1" "F:/adc_1/db/adc_1.quartus_db" { Floorplan "F:/adc_1/" "" "2.400 ns" { reset beg } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.400 ns" { reset reset~out beg } { 0.000ns 0.000ns 2.000ns } { 0.000ns 0.300ns 0.100ns } } }  } 0}  } { { "F:/adc_1/db/adc_1_cmp.qrpt" "" { Report "F:/adc_1/db/adc_1_cmp.qrpt" Compiler "adc_1" "UNKNOWN" "V1" "F:/adc_1/db/adc_1.quartus_db" { Floorplan "F:/adc_1/" "" "1.100 ns" { clk beg } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "1.100 ns" { clk clk~out beg } { 0.000ns 0.000ns 0.800ns } { 0.000ns 0.300ns 0.000ns } } } { "F:/adc_1/db/adc_1_cmp.qrpt" "" { Report "F:/adc_1/db/adc_1_cmp.qrpt" Compiler "adc_1" "UNKNOWN" "V1" "F:/adc_1/db/adc_1.quartus_db" { Floorplan "F:/adc_1/" "" "2.400 ns" { reset beg } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.400 ns" { reset reset~out beg } { 0.000ns 0.000ns 2.000ns } { 0.000ns 0.300ns 0.100ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Dec 06 16:58:19 2007 " "Info: Processing ended: Thu Dec 06 16:58:19 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}
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